/freebsd-9.3-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 82 @i32["mouse", -2] = sum(-2); 83 @i32["bear", -2] = sum(-22); 84 @i32["cat", -2] = sum(-222); 85 @i32["mouse", -1] = sum(-1); 86 @i32["bear", -1] = sum(-11); 87 @i32["cat", -1] = sum(-111); 88 @i32["mouse", 0] = sum(0); 89 @i32["bear", 0] = sum(10); 90 @i32["cat", 0] = sum(100); 91 @i32["mous [all...] |
H A D | tst.signedkeys.d | 107 @i32[-2] = sum(-2); 108 @i32[-1] = sum(-1); 109 @i32[0] = sum(0); 110 @i32[1] = sum(1); 111 @i32[2] = sum(2);
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/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 51 /// i32. 53 return CurDAG->getTargetConstant(Imm, MVT::i32); 91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 92 Offset = CurDAG->getTargetConstant(0, MVT::i32); 101 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 102 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); 120 MVT::i32, MskSize); 127 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 141 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, [all...] |
H A D | XCoreISelLowering.cpp | 73 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 85 // Use i32 for setcc operations results (slt, sgt, ...). 90 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 91 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 92 setOperationAction(ISD::ADDC, MVT::i32, Expand); 93 setOperationAction(ISD::ADDE, MVT::i32, Expand); 94 setOperationAction(ISD::SUBC, MVT::i32, Expand); 95 setOperationAction(ISD::SUBE, MVT::i32, Expand); 103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 104 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custo [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32; 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 68 DAG.getConstant(SrcOff, MVT::i32)), 79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 80 DAG.getConstant(DstOff, MVT::i32)), 106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 107 DAG.getConstant(SrcOff, MVT::i32)), 129 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 130 DAG.getConstant(DstOff, MVT::i32)), 169 // Extend or truncate the argument to be an i32 valu [all...] |
H A D | ARMISelDAGToDAG.cpp | 82 /// getI32Imm - Return a target constant of type i32 with the specified 85 return CurDAG->getTargetConstant(Imm, MVT::i32); 135 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); 136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); 283 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 396 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, 398 CurDAG->getConstant(Srl_imm+TZ, MVT::i32)); 399 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32, 400 Srl, CurDAG->getConstant(And_imm, MVT::i32)); 401 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32, [all...] |
H A D | ARMISelLowering.cpp | 109 if (ElemTy == MVT::i32) { 433 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); 435 addRegisterClass(MVT::i32, &ARM::GPRRegClass); 633 setIndexedLoadAction(im, MVT::i32, Legal); 637 setIndexedStoreAction(im, MVT::i32, Legal); 643 setOperationAction(ISD::MULHU, MVT::i32, Expand); 645 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 646 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 650 setOperationAction(ISD::MULHS, MVT::i32, Expand); 652 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custo [all...] |
/freebsd-9.3-release/sys/i386/i386/ |
H A D | bpf_jit_machdep.h | 108 /* movl i32,r32 */ 109 #define MOVid(i32, r32) do { \ 111 emitm(&stream, i32, 4); \ 195 /* addl i32,%eax */ 196 #define ADD_EAXi(i32) do { \ 198 emitm(&stream, i32, 4); \ 215 /* subl i32,%eax */ 216 #define SUB_EAXi(i32) do { \ 218 emitm(&stream, i32, 4); \ 251 /* andl i32,r3 [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPUISelDAGToDAG.cpp | 138 return CurDAG->getTargetConstant(Imm, MVT::i32); 146 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 147 R2 = CurDAG->getTargetConstant(0, MVT::i32); 150 R2 = CurDAG->getTargetConstant(0, MVT::i32); 157 R2 = CurDAG->getTargetConstant(0, MVT::i32); 212 assert(VT.getVectorElementType().bitsEq(MVT::i32)); 258 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32); 273 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32); 283 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32); 297 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32); [all...] |
H A D | R600ISelLowering.cpp | 35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); 55 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); 56 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); 57 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); 58 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); 66 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 76 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 78 setOperationAction(ISD::SETCC, MVT::i32, Expand); 82 setOperationAction(ISD::SELECT, MVT::i32, Expand); 90 setOperationAction(ISD::LOAD, MVT::i32, Custo [all...] |
H A D | SIISelLowering.cpp | 40 addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass); 80 setOperationAction(ISD::ADD, MVT::i32, Legal); 81 setOperationAction(ISD::ADDC, MVT::i32, Legal); 82 setOperationAction(ISD::ADDE, MVT::i32, Legal); 96 setOperationAction(ISD::LOAD, MVT::i32, Custom); 101 setOperationAction(ISD::STORE, MVT::i32, Custom); 109 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 127 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand); 128 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand); 134 setTruncStoreAction(MVT::i64, MVT::i32, Expan [all...] |
H A D | AMDILISelLowering.cpp | 45 (int)MVT::i32, 64 (int)MVT::i32, 206 setOperationAction(ISD::Constant , MVT::i32 , Legal); 296 } else if (OVT.getScalarType() == MVT::i32) { 313 } else if (OVT.getScalarType() == MVT::i32) { 370 return EVT(MVT::i32); 372 return EVT(MVT::getVectorVT(MVT::i32, vEle)); 400 INTTY = MVT::i32; 458 if (INTTY == MVT::i32) { 501 DAG.getConstant(-1, MVT::i32), [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 122 return CurDAG->getTargetConstant(bitPos, MVT::i32); 146 // i32 where the negative literal is transformed into a positive literal for 150 return CurDAG->getTargetConstant( - Imm, MVT::i32); 163 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); 169 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); 368 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) { 407 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; 447 N1.getNode()->getValueType(0) == MVT::i32) { 451 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32); 452 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MV [all...] |
H A D | HexagonISelLowering.cpp | 119 LocVT = MVT::i32; 120 ValVT = MVT::i32; 128 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 157 LocVT = MVT::i32; 158 ValVT = MVT::i32; 167 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 232 LocVT = MVT::i32; 233 ValVT = MVT::i32; 242 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 259 if (LocVT == MVT::i32 || LocV [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 79 Offset = CurDAG->getTargetConstant(0, MVT::i32); 98 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); 114 Offset = CurDAG->getTargetConstant(0, MVT::i32); 166 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, 167 CurDAG->getTargetConstant(31, MVT::i32)), 0); 169 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 172 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 176 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 185 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue, 188 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValu [all...] |
H A D | SparcISelLowering.cpp | 139 if (LocVT == MVT::i32 && Offset < 6*8) { 145 // Set the Custom bit if this i32 goes in the high bits of a register. 232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 265 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 287 // The custom bit on an i32 return value indicates that it should be passed 289 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 291 DAG.getConstant(32, MVT::i32)); 364 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 365 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 377 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 73 /// i32. 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 263 if (PPCLowering.getPointerTy() == MVT::i32) { 286 if (N->getValueType(0) == MVT::i32) 300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 361 if (N->getValueType(0) != MVT::i32) 463 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 476 if (LHS.getValueType() == MVT::i32) { 482 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 486 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LH [all...] |
H A D | PPCISelLowering.cpp | 75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 110 setOperationAction(ISD::SREM, MVT::i32, Expand); 111 setOperationAction(ISD::UREM, MVT::i32, Expand); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custo [all...] |
/freebsd-9.3-release/sys/amd64/amd64/ |
H A D | bpf_jit_machdep.h | 133 /* movl i32,r32 */ 134 #define MOVid(i32, r32) do { \ 136 emitm(&stream, i32, 4); \ 250 /* addl i32,%eax */ 251 #define ADD_EAXi(i32) do { \ 253 emitm(&stream, i32, 4); \ 270 /* subl i32,%eax */ 271 #define SUB_EAXi(i32) do { \ 273 emitm(&stream, i32, 4); \ 306 /* andl i32,r3 [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 264 case MVT::i32: 293 case MVT::i32: 323 case MVT::i32: 346 case MVT::i32: 375 case MVT::i32: 398 case MVT::i32: 506 case MVT::i32: 530 case MVT::i32: 560 case MVT::i32: 584 case MVT::i32 [all...] |
H A D | NVPTXISelLowering.cpp | 127 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); 139 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 157 setOperationAction(ISD::ROTL, MVT::i32, Legal); 158 setOperationAction(ISD::ROTR, MVT::i32, Legal); 160 setOperationAction(ISD::ROTL, MVT::i32, Expand); 161 setOperationAction(ISD::ROTR, MVT::i32, Expand); 169 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 177 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 196 setTruncStoreAction(MVT::i32, MV [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 184 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); 185 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, 186 DAG.getConstant(SystemZ::IPM_CC, MVT::i32)); 187 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, 188 DAG.getConstant(31, MVT::i32)); 215 Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32); 216 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, 217 DAG.getConstant(255, MVT::i32)); 229 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32)); 230 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32)); [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 210 // Mips does not have i1 type, so use i32 for 228 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 232 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 233 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 234 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 235 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 236 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 239 setOperationAction(ISD::SELECT, MVT::i32, Custom); 248 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 268 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custo [all...] |
H A D | Mips16ISelLowering.cpp | 123 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 135 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 136 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 142 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expan [all...] |
/freebsd-9.3-release/sys/geom/vinum/ |
H A D | geom_vinum_drive.c | 76 uint32_t *i32; local 89 i32 = (uint32_t *)(hdr + 12); 90 if (*i32 != 0) 100 i32 = (uint32_t *)(hdr + 84); 102 if (*i32 == 0)
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