/freebsd-9.3-release/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 33 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:llvm::AMDGPUMCCodeEmitter
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H A D | R600MCCodeEmitter.cpp | 50 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 169 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:R600MCCodeEmitter
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H A D | SIMCCodeEmitter.cpp | 61 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 169 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:SIMCCodeEmitter
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 48 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 106 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SystemZMCCodeEmitter 118 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); 119 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); 127 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); 128 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); 136 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); 137 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); 138 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); 146 uint64_t Base = getMachineOpValue(M [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 69 /// getMachineOpValue - Return binary encoding of operand. If the machine 71 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 120 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 131 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 143 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 155 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 166 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 179 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; 183 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; 197 unsigned RegBits = getMachineOpValue(M 246 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:PPCMCCodeEmitter [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 50 /// getMachineOpValue - Return binary encoding of operand. If the machine 52 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 91 uint64_t op = getMachineOpValue(MI, MO, Fixups); 101 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:SparcMCCodeEmitter 131 return getMachineOpValue(MI, MO, Fixups); 165 return getMachineOpValue(MI, MO, Fixups);
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 60 unsigned getMachineOpValue(const MachineInstr &MI, 187 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 203 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 216 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 234 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; 238 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; 250 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; 254 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits; 273 unsigned PPCCodeEmitter::getMachineOpValue(cons function in class:PPCCodeEmitter [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 150 unsigned getMachineOpValue(const MachineInstr &MI, 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { function in class:__anon2319::ARMCodeEmitter 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 // operand values, instead querying getMachineOpValue() directly for 450 /// getMachineOpValue - Return binary encoding of operand. If the machine 452 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:ARMCodeEmitter 708 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 723 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 746 Binary |= getMachineOpValue(M [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcCodeEmitter.cpp | 70 /// getMachineOpValue - Return binary encoding of operand. If the machine 72 unsigned getMachineOpValue(const MachineInstr &MI, 169 /// getMachineOpValue - Return binary encoding of operand. If the machine 171 unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:SparcCodeEmitter 192 return getMachineOpValue(MI, MO); 198 return getMachineOpValue(MI, MO);
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsCodeEmitter.cpp | 99 /// getMachineOpValue - Return binary encoding of operand. If the machine 101 unsigned getMachineOpValue(const MachineInstr &MI, 217 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; 218 return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; 230 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 236 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + 237 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 246 /// getMachineOpValue - Return binary encoding of operand. If the machine 248 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, function in class:MipsCodeEmitter
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 105 // getMachineOpValue - Return binary encoding of operand. If the machin 107 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 463 /// getMachineOpValue - Return binary encoding of operand. If the machine 466 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 490 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; 491 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); 501 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16; 502 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); 511 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); 522 unsigned Position = getMachineOpValue(M [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 104 /// getMachineOpValue - Return binary encoding of operand. If the machine 106 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 409 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, function in class:AArch64MCCodeEmitter
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 71 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 415 /// getMachineOpValue - Return binary encoding of operand. If the machine 418 getMachineOpValue(const MCInst &MI, const MCOperand &MO, function in class:ARMMCCodeEmitter
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