1226584Sdim//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim// 10226584Sdim// This file implements the PPCMCCodeEmitter class. 11226584Sdim// 12226584Sdim//===----------------------------------------------------------------------===// 13226584Sdim 14226584Sdim#define DEBUG_TYPE "mccodeemitter" 15252723Sdim#include "MCTargetDesc/PPCMCTargetDesc.h" 16226584Sdim#include "MCTargetDesc/PPCFixupKinds.h" 17252723Sdim#include "llvm/ADT/Statistic.h" 18226584Sdim#include "llvm/MC/MCCodeEmitter.h" 19252723Sdim#include "llvm/MC/MCContext.h" 20252723Sdim#include "llvm/MC/MCExpr.h" 21226584Sdim#include "llvm/MC/MCInst.h" 22245431Sdim#include "llvm/MC/MCInstrInfo.h" 23252723Sdim#include "llvm/MC/MCSubtargetInfo.h" 24252723Sdim#include "llvm/Support/ErrorHandling.h" 25226584Sdim#include "llvm/Support/raw_ostream.h" 26263509Sdim#include "llvm/Target/TargetOpcodes.h" 27226584Sdimusing namespace llvm; 28226584Sdim 29226584SdimSTATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 30226584Sdim 31226584Sdimnamespace { 32226584Sdimclass PPCMCCodeEmitter : public MCCodeEmitter { 33245431Sdim PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; 34245431Sdim void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; 35245431Sdim 36245431Sdim const MCSubtargetInfo &STI; 37252723Sdim const MCContext &CTX; 38245431Sdim Triple TT; 39245431Sdim 40226584Sdimpublic: 41226584Sdim PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 42245431Sdim MCContext &ctx) 43252723Sdim : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) { 44226584Sdim } 45226584Sdim 46226584Sdim ~PPCMCCodeEmitter() {} 47226584Sdim 48226584Sdim unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 49226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 50226584Sdim unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 51226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 52263509Sdim unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 53263509Sdim SmallVectorImpl<MCFixup> &Fixups) const; 54263509Sdim unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 55263509Sdim SmallVectorImpl<MCFixup> &Fixups) const; 56263509Sdim unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 57263509Sdim SmallVectorImpl<MCFixup> &Fixups) const; 58226584Sdim unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 59226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 60226584Sdim unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 61226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 62252723Sdim unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 63252723Sdim SmallVectorImpl<MCFixup> &Fixups) const; 64263509Sdim unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 65263509Sdim SmallVectorImpl<MCFixup> &Fixups) const; 66226584Sdim unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 67226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 68226584Sdim 69226584Sdim /// getMachineOpValue - Return binary encoding of operand. If the machine 70226584Sdim /// operand requires relocation, record the relocation and return zero. 71226584Sdim unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 72226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 73226584Sdim 74226584Sdim // getBinaryCodeForInstr - TableGen'erated function for getting the 75226584Sdim // binary encoding for an instruction. 76235633Sdim uint64_t getBinaryCodeForInstr(const MCInst &MI, 77226584Sdim SmallVectorImpl<MCFixup> &Fixups) const; 78226584Sdim void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 79226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 80263509Sdim // For fast-isel, a float COPY_TO_REGCLASS can survive this long. 81263509Sdim // It's just a nop to keep the register classes happy, so don't 82263509Sdim // generate anything. 83263509Sdim unsigned Opcode = MI.getOpcode(); 84263509Sdim if (Opcode == TargetOpcode::COPY_TO_REGCLASS) 85263509Sdim return; 86263509Sdim 87245431Sdim uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); 88245431Sdim 89252723Sdim // BL8_NOP etc. all have a size of 8 because of the following 'nop'. 90245431Sdim unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value! 91252723Sdim if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP || 92263509Sdim Opcode == PPC::BL8_NOP_TLS) 93245431Sdim Size = 8; 94226584Sdim 95226584Sdim // Output the constant in big endian byte order. 96245431Sdim int ShiftValue = (Size * 8) - 8; 97245431Sdim for (unsigned i = 0; i != Size; ++i) { 98245431Sdim OS << (char)(Bits >> ShiftValue); 99226584Sdim Bits <<= 8; 100226584Sdim } 101226584Sdim 102226584Sdim ++MCNumEmitted; // Keep track of the # of mi's emitted. 103226584Sdim } 104226584Sdim 105226584Sdim}; 106226584Sdim 107226584Sdim} // end anonymous namespace 108226584Sdim 109226584SdimMCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 110245431Sdim const MCRegisterInfo &MRI, 111226584Sdim const MCSubtargetInfo &STI, 112226584Sdim MCContext &Ctx) { 113226584Sdim return new PPCMCCodeEmitter(MCII, STI, Ctx); 114226584Sdim} 115226584Sdim 116226584Sdimunsigned PPCMCCodeEmitter:: 117226584SdimgetDirectBrEncoding(const MCInst &MI, unsigned OpNo, 118226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 119226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 120226584Sdim if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 121226584Sdim 122226584Sdim // Add a fixup for the branch target. 123226584Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 124226584Sdim (MCFixupKind)PPC::fixup_ppc_br24)); 125226584Sdim return 0; 126226584Sdim} 127226584Sdim 128226584Sdimunsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 129226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 130226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 131226584Sdim if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 132226584Sdim 133226584Sdim // Add a fixup for the branch target. 134226584Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 135226584Sdim (MCFixupKind)PPC::fixup_ppc_brcond14)); 136226584Sdim return 0; 137226584Sdim} 138226584Sdim 139263509Sdimunsigned PPCMCCodeEmitter:: 140263509SdimgetAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 141263509Sdim SmallVectorImpl<MCFixup> &Fixups) const { 142226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 143226584Sdim if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 144263509Sdim 145226584Sdim // Add a fixup for the branch target. 146226584Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 147263509Sdim (MCFixupKind)PPC::fixup_ppc_br24abs)); 148226584Sdim return 0; 149226584Sdim} 150226584Sdim 151263509Sdimunsigned PPCMCCodeEmitter:: 152263509SdimgetAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 153263509Sdim SmallVectorImpl<MCFixup> &Fixups) const { 154226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 155226584Sdim if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 156263509Sdim 157226584Sdim // Add a fixup for the branch target. 158226584Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 159263509Sdim (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 160226584Sdim return 0; 161226584Sdim} 162226584Sdim 163263509Sdimunsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 164263509Sdim SmallVectorImpl<MCFixup> &Fixups) const { 165263509Sdim const MCOperand &MO = MI.getOperand(OpNo); 166263509Sdim if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 167263509Sdim 168263509Sdim // Add a fixup for the immediate field. 169263509Sdim Fixups.push_back(MCFixup::Create(2, MO.getExpr(), 170263509Sdim (MCFixupKind)PPC::fixup_ppc_half16)); 171263509Sdim return 0; 172263509Sdim} 173263509Sdim 174226584Sdimunsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 175226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 176226584Sdim // Encode (imm, reg) as a memri, which has the low 16-bits as the 177226584Sdim // displacement and the next 5 bits as the register #. 178226584Sdim assert(MI.getOperand(OpNo+1).isReg()); 179226584Sdim unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; 180226584Sdim 181226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 182226584Sdim if (MO.isImm()) 183226584Sdim return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; 184226584Sdim 185226584Sdim // Add a fixup for the displacement field. 186263509Sdim Fixups.push_back(MCFixup::Create(2, MO.getExpr(), 187263509Sdim (MCFixupKind)PPC::fixup_ppc_half16)); 188226584Sdim return RegBits; 189226584Sdim} 190226584Sdim 191226584Sdim 192226584Sdimunsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 193226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 194226584Sdim // Encode (imm, reg) as a memrix, which has the low 14-bits as the 195226584Sdim // displacement and the next 5 bits as the register #. 196226584Sdim assert(MI.getOperand(OpNo+1).isReg()); 197226584Sdim unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; 198226584Sdim 199226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 200226584Sdim if (MO.isImm()) 201263509Sdim return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits; 202226584Sdim 203252723Sdim // Add a fixup for the displacement field. 204263509Sdim Fixups.push_back(MCFixup::Create(2, MO.getExpr(), 205263509Sdim (MCFixupKind)PPC::fixup_ppc_half16ds)); 206226584Sdim return RegBits; 207226584Sdim} 208226584Sdim 209226584Sdim 210252723Sdimunsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 211252723Sdim SmallVectorImpl<MCFixup> &Fixups) const { 212252723Sdim const MCOperand &MO = MI.getOperand(OpNo); 213252723Sdim if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups); 214252723Sdim 215252723Sdim // Add a fixup for the TLS register, which simply provides a relocation 216252723Sdim // hint to the linker that this statement is part of a relocation sequence. 217252723Sdim // Return the thread-pointer register's encoding. 218252723Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 219263509Sdim (MCFixupKind)PPC::fixup_ppc_nofixup)); 220263509Sdim return CTX.getRegisterInfo()->getEncodingValue(PPC::X13); 221252723Sdim} 222252723Sdim 223263509Sdimunsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 224263509Sdim SmallVectorImpl<MCFixup> &Fixups) const { 225263509Sdim // For special TLS calls, we need two fixups; one for the branch target 226263509Sdim // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 227263509Sdim // and one for the TLSGD or TLSLD symbol, which is emitted here. 228263509Sdim const MCOperand &MO = MI.getOperand(OpNo+1); 229263509Sdim Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 230263509Sdim (MCFixupKind)PPC::fixup_ppc_nofixup)); 231263509Sdim return getDirectBrEncoding(MI, OpNo, Fixups); 232263509Sdim} 233263509Sdim 234226584Sdimunsigned PPCMCCodeEmitter:: 235226584Sdimget_crbitm_encoding(const MCInst &MI, unsigned OpNo, 236226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 237226584Sdim const MCOperand &MO = MI.getOperand(OpNo); 238263509Sdim assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 239263509Sdim MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 240226584Sdim (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 241263509Sdim return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 242226584Sdim} 243226584Sdim 244226584Sdim 245226584Sdimunsigned PPCMCCodeEmitter:: 246226584SdimgetMachineOpValue(const MCInst &MI, const MCOperand &MO, 247226584Sdim SmallVectorImpl<MCFixup> &Fixups) const { 248226584Sdim if (MO.isReg()) { 249263509Sdim // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 250226584Sdim // The GPR operand should come through here though. 251263509Sdim assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 252263509Sdim MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 253226584Sdim MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 254263509Sdim return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 255226584Sdim } 256226584Sdim 257226584Sdim assert(MO.isImm() && 258226584Sdim "Relocation required in an instruction that we cannot encode!"); 259226584Sdim return MO.getImm(); 260226584Sdim} 261226584Sdim 262226584Sdim 263226584Sdim#include "PPCGenMCCodeEmitter.inc" 264