Searched refs:OS_REG_READ (Results 1 - 25 of 82) sorted by relevance

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/freebsd-9.3-release/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_eeprom.c37 OS_REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
41 *data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA),
H A Dar5416_gpio.c64 reg = OS_REG_READ(ah, addr);
86 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
108 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
126 reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
150 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
152 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
154 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
170 val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
175 mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
181 val = MS(OS_REG_READ(a
[all...]
H A Dar5416_interrupts.c45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
77 isr = OS_REG_READ(ah, AR_ISR);
79 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
80 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
81 isr = OS_REG_READ(ah, AR_ISR);
84 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
98 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
115 isr = OS_REG_READ(ah, AR_ISR_RAC);
126 isr0 = OS_REG_READ(a
[all...]
H A Dar5416_misc.c83 bits = OS_REG_READ(ah, AR_MAC_LED);
104 low1 = OS_REG_READ(ah, AR_TSF_L32);
105 u32 = OS_REG_READ(ah, AR_TSF_U32);
106 low2 = OS_REG_READ(ah, AR_TSF_L32);
140 v = OS_REG_READ(ah, AR_SLP32_MODE);
180 ctlBusy = OS_REG_READ(ah, AR_RCCNT);
181 extBusy = OS_REG_READ(ah, AR_EXTRCCNT);
182 cycleCount = OS_REG_READ(ah, AR_CCCNT);
274 val = OS_REG_READ(ah, AR_DIAG_SW);
323 nextStart_us += OS_REG_READ(a
[all...]
H A Dar5416_cal_adcdc.c43 OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
45 OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
47 OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
49 OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
101 val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
H A Dar5416_cal_adcgain.c49 OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
51 OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
53 OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
55 OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
105 val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
/freebsd-9.3-release/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_interrupts.c42 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE);
61 isr = OS_REG_READ(ah, AR_ISR);
64 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
76 isr = OS_REG_READ(ah, AR_ISR_RAC);
90 isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
93 isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
115 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
116 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
117 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
118 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(a
[all...]
H A Dar5212_recv.c34 return OS_REG_READ(ath, AR_RXDP);
44 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
70 OS_REG_READ(ah, AR_CR),
71 OS_REG_READ(ah, AR_DIAG_SW));
89 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
103 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
129 val = OS_REG_READ(ah, AR_MCAST_FIL1);
132 val = OS_REG_READ(ah, AR_MCAST_FIL0);
149 val = OS_REG_READ(ah, AR_MCAST_FIL1);
152 val = OS_REG_READ(a
[all...]
H A Dar5212_gpio.c48 OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
62 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
78 reg = OS_REG_READ(ah, AR_GPIODO);
93 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
110 val = OS_REG_READ(ah, AR_GPIOCR);
H A Dar5212_eeprom.c48 *data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
H A Dar5212_power.c57 scr = OS_REG_READ(ah, AR_SCR);
61 __func__, scr, OS_REG_READ(ah, AR_PCICFG));
69 val = OS_REG_READ(ah, AR_PCICFG);
162 return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
173 return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;
/freebsd-9.3-release/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_recv.c35 return OS_REG_READ(ah, AR_RXDP);
45 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
70 , OS_REG_READ(ah, AR_CR)
71 , OS_REG_READ(ah, AR_DIAG_SW)
87 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
97 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
122 val = OS_REG_READ(ah, AR_MCAST_FIL1);
125 val = OS_REG_READ(ah, AR_MCAST_FIL0);
142 val = OS_REG_READ(ah, AR_MCAST_FIL1);
145 val = OS_REG_READ(a
[all...]
H A Dar5211_interrupts.c36 return OS_REG_READ(ah, AR_INTPEND) != 0;
53 isr = OS_REG_READ(ah, AR_ISR_RAC);
83 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
84 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
85 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
86 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
87 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
124 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */
H A Dar5211_beacon.c39 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
108 val = OS_REG_READ(ah, AR_STA_ID1);
133 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
146 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
162 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
H A Dar5211_misc.c80 *data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
201 reg = OS_REG_READ(ah, AR_GPIOCR);
219 reg = OS_REG_READ(ah, AR_GPIOCR);
237 reg = OS_REG_READ(ah, AR_GPIODO);
252 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
266 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
300 (OS_REG_READ(ah, AR_PCICFG) &~
333 low1 = OS_REG_READ(ah, AR_TSF_L32);
334 u32 = OS_REG_READ(ah, AR_TSF_U32);
335 low2 = OS_REG_READ(a
[all...]
/freebsd-9.3-release/sys/dev/ath/ath_hal/ar5210/
H A Dar5210_misc.c70 (void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */
77 *data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
166 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
181 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
197 reg = OS_REG_READ(ah, AR_GPIODO);
212 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
226 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
251 val = OS_REG_READ(ah, AR_PCICFG);
275 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
282 uint32_t val = OS_REG_READ(a
[all...]
H A Dar5210_recv.c35 return OS_REG_READ(ah, AR_RXDP);
67 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
73 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
74 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
86 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
96 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
121 val = OS_REG_READ(ah, AR_MCAST_FIL1);
124 val = OS_REG_READ(ah, AR_MCAST_FIL0);
141 val = OS_REG_READ(ah, AR_MCAST_FIL1);
144 val = OS_REG_READ(a
[all...]
H A Dar5210_beacon.c36 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
99 val = OS_REG_READ(ah, AR_STA_ID1);
127 (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
141 OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
157 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
/freebsd-9.3-release/sys/dev/ath/ath_hal/ar5312/
H A Dar5315_gpio.c45 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
62 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
79 reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);
96 uint32_t val = OS_REG_READ(ah, gpioOffset+AR5315_GPIODI);
114 val = OS_REG_READ(ah, gpioOffset+AR5315_GPIOINT);
H A Dar5312_gpio.c45 (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
62 (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
79 reg = OS_REG_READ(ah, gpioOffset+AR5312_GPIODO);
96 uint32_t val = OS_REG_READ(ah, gpioOffset+AR5312_GPIODI);
114 val = OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR);
/freebsd-9.3-release/tools/tools/ath/athregs/
H A Ddumpregs.c57 #undef OS_REG_READ macro
58 #define OS_REG_READ(ah, off) state.regdata[(off) >> 2] macro
454 fprintf(fd, " %08x", OS_REG_READ(ah, dr->addr));
472 , r, OS_REG_READ(ah, r)
473 , r+4, OS_REG_READ(ah, r+4)
474 , r+8, OS_REG_READ(ah, r+8)
475 , r+12, OS_REG_READ(ah, r+12)
476 , r+16, OS_REG_READ(ah, r+16)
482 , r, OS_REG_READ(ah, r)
483 , r+4, OS_REG_READ(a
[all...]
/freebsd-9.3-release/sys/dev/ath/ath_hal/ar9002/
H A Dar9285_cal.c72 regList[i][1] = OS_REG_READ(ah, regList[i][0]);
74 regVal = OS_REG_READ(ah, 0x7834);
77 regVal = OS_REG_READ(ah, 0x9808);
93 ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
102 regVal = OS_REG_READ(ah, 0x7834);
106 regVal = OS_REG_READ(ah, 0x7834);
108 reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
115 reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
117 offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
118 offs_0 = MS(OS_REG_READ(a
[all...]
H A Dar9285.c46 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
54 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
H A Dar9287_cal.c59 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
H A Dar9287_olc.c70 rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);
140 tmpVal = OS_REG_READ(ah, 0xa270);
147 tmpVal = OS_REG_READ(ah, 0xb270);
155 tmpVal = OS_REG_READ(ah, 0xa398);
165 tmpVal = OS_REG_READ(ah, 0xb398);

Completed in 190 milliseconds

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