1185380Ssam/* 2185380Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185380Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185380Ssam * 5185380Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185380Ssam * purpose with or without fee is hereby granted, provided that the above 7185380Ssam * copyright notice and this permission notice appear in all copies. 8185380Ssam * 9185380Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185380Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185380Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185380Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185380Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185380Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185380Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185380Ssam * 17203158Srpaulo * $FreeBSD$ 18185380Ssam */ 19185380Ssam#include "opt_ah.h" 20185380Ssam 21185380Ssam#include "ah.h" 22185380Ssam#include "ah_internal.h" 23185380Ssam#include "ah_devid.h" 24185380Ssam 25185380Ssam#include "ar5416/ar5416.h" 26185380Ssam#include "ar5416/ar5416reg.h" 27185380Ssam#include "ar5416/ar5416phy.h" 28185380Ssam 29185380Ssam/* Adc DC Offset Cal aliases */ 30185380Ssam#define totalAdcDcOffsetIOddPhase(i) caldata[0][i].s 31185380Ssam#define totalAdcDcOffsetIEvenPhase(i) caldata[1][i].s 32185380Ssam#define totalAdcDcOffsetQOddPhase(i) caldata[2][i].s 33185380Ssam#define totalAdcDcOffsetQEvenPhase(i) caldata[3][i].s 34185380Ssam 35185380Ssamvoid 36185380Ssamar5416AdcDcCalCollect(struct ath_hal *ah) 37185380Ssam{ 38185380Ssam struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; 39185380Ssam int i; 40185380Ssam 41185380Ssam for (i = 0; i < AR5416_MAX_CHAINS; i++) { 42185380Ssam cal->totalAdcDcOffsetIOddPhase(i) += (int32_t) 43185380Ssam OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 44185380Ssam cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t) 45185380Ssam OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 46185380Ssam cal->totalAdcDcOffsetQOddPhase(i) += (int32_t) 47185380Ssam OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 48185380Ssam cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t) 49185380Ssam OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 50185380Ssam 51185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 52185380Ssam "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", 53185380Ssam cal->calSamples, i, 54185380Ssam cal->totalAdcDcOffsetIOddPhase(i), 55185380Ssam cal->totalAdcDcOffsetIEvenPhase(i), 56185380Ssam cal->totalAdcDcOffsetQOddPhase(i), 57185380Ssam cal->totalAdcDcOffsetQEvenPhase(i)); 58185380Ssam } 59185380Ssam} 60185380Ssam 61185380Ssamvoid 62185380Ssamar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains) 63185380Ssam{ 64185380Ssam struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; 65185380Ssam const HAL_PERCAL_DATA *calData = cal->cal_curr->calData; 66185380Ssam uint32_t numSamples; 67185380Ssam int i; 68185380Ssam 69185380Ssam numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples; 70185380Ssam for (i = 0; i < numChains; i++) { 71185380Ssam uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i); 72185380Ssam uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i); 73185380Ssam int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i); 74185380Ssam int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i); 75185380Ssam int32_t qDcMismatch, iDcMismatch; 76185380Ssam uint32_t val; 77185380Ssam 78185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 79185380Ssam "Starting ADC DC Offset Cal for Chain %d\n", i); 80185380Ssam 81185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n", 82185380Ssam iOddMeasOffset); 83185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n", 84185380Ssam iEvenMeasOffset); 85185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n", 86185380Ssam qOddMeasOffset); 87185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n", 88185380Ssam qEvenMeasOffset); 89185380Ssam 90185380Ssam HALASSERT(numSamples); 91185380Ssam 92185380Ssam iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 93185380Ssam numSamples) & 0x1ff; 94185380Ssam qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 95185380Ssam numSamples) & 0x1ff; 96185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 97185380Ssam " dc_offset_mismatch_i = 0x%08x\n", iDcMismatch); 98185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 99185380Ssam " dc_offset_mismatch_q = 0x%08x\n", qDcMismatch); 100185380Ssam 101185380Ssam val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 102185380Ssam val &= 0xc0000fff; 103185380Ssam val |= (qDcMismatch << 12) | (iDcMismatch << 21); 104185380Ssam OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 105185380Ssam 106185380Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 107185380Ssam "ADC DC Offset Cal done for Chain %d\n", i); 108185380Ssam } 109185380Ssam OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 110185380Ssam AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE); 111185380Ssam} 112