/freebsd-9.3-release/contrib/binutils/ld/ |
H A D | ldlex.l | 82 MRI in an MRI script 117 %s MRI 147 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ { 153 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) { 178 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? { 207 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');} 208 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');} 209 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);} 210 <BOTH,SCRIPT,EXPRESSION,MRI>">> [all...] |
/freebsd-9.3-release/contrib/llvm/include/llvm/MC/ |
H A D | MCModuleYAML.h | 32 const MCInstrInfo &MII, const MCRegisterInfo &MRI); 37 const MCInstrInfo &MII, const MCRegisterInfo &MRI);
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/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | SIFixSGPRCopies.cpp | 87 const MachineRegisterInfo &MRI, 91 const MachineRegisterInfo &MRI, 95 const MachineRegisterInfo &MRI) const; 117 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local 123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 134 const MachineRegisterInfo &MRI, 142 const TargetRegisterClass *RC = MRI.getRegClass(Reg); 144 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), 145 E = MRI.use_end(); I != E; ++I) { 148 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 132 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 158 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 195 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.h | 37 const MCRegisterInfo &MRI, 41 const MCRegisterInfo &MRI, 45 MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, 47 MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, 49 MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, 51 MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI,
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
H A D | RegAllocBase.cpp | 60 MRI = &vrm.getRegInfo(); 64 MRI->freezeReservedRegs(vrm.getMachineFunction()); 73 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 75 if (MRI->reg_nodbg_empty(Reg)) 91 if (MRI->reg_nodbg_empty(VirtReg->reg)) { 104 << MRI->getRegClass(VirtReg->reg)->getName() 114 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg); 124 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); 135 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
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H A D | PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); local 37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), 38 RE = MRI.reg_end(); RI != RE; ++RI) {
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H A D | VirtRegMap.cpp | 54 MRI = &mf.getRegInfo(); 82 unsigned Hint = MRI->getSimpleHint(VirtReg); 91 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 119 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 124 << MRI->getRegClass(Reg)->getName() << "\n"; 128 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 132 << "] " << MRI->getRegClass(Reg)->getName() << "\n"; 159 MachineRegisterInfo *MRI; member in class:__anon2210::VirtRegRewriter 207 MRI = &MF->getRegInfo(); 231 MRI [all...] |
H A D | OptimizePHIs.cpp | 31 MachineRegisterInfo *MRI; member in class:__anon2159::OptimizePHIs 64 MRI = &Fn.getRegInfo(); 102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg), 143 E = MRI->use_end(); I != E; ++I) { 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) 171 MRI->replaceRegWith(OldReg, SingleValReg);
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H A D | RegAllocBase.h | 63 MachineRegisterInfo *MRI; member in class:llvm::RegAllocBase 69 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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H A D | DeadMachineInstructionElim.cpp | 33 const MachineRegisterInfo *MRI; member in class:__anon2114::DeadMachineInstructionElim 72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) 75 if (!MRI->use_nodbg_empty(Reg)) 88 MRI = &MF.getRegInfo(); 100 LivePhysRegs = MRI->getReservedRegs(); 131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), 132 E = MRI->use_end(); I!=E; I=nextI) {
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H A D | PeepholeOptimizer.cpp | 104 MachineRegisterInfo *MRI; member in class:__anon2161::PeepholeOptimizer 168 if (MRI->hasOneNonDBGUse(SrcReg)) 174 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 185 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 191 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); 203 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); 274 UI = MRI->use_nodbg_begin(DstReg), UE = MRI [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.h | 35 const MCRegisterInfo &MRI, 39 const MCRegisterInfo &MRI, 43 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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H A D | AMDGPUMCTargetDesc.cpp | 69 const MCRegisterInfo &MRI, 71 return new AMDGPUInstPrinter(MAI, MII, MRI); 75 const MCRegisterInfo &MRI, 79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 81 return createR600MCCodeEmitter(MCII, MRI, STI); 65 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 74 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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H A D | R600MCCodeEmitter.cpp | 36 const MCRegisterInfo &MRI; member in class:__anon2449::R600MCCodeEmitter 43 : MCII(mcii), MRI(mri), STI(sti) { } 84 const MCRegisterInfo &MRI, 86 return new R600MCCodeEmitter(MCII, MRI, STI); 162 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT; 166 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; 174 return MRI.getEncodingValue(MO.getReg()); 83 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.h | 39 const MCRegisterInfo &MRI, 47 const MCRegisterInfo &MRI,
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.h | 25 const MCRegisterInfo &MRI) 26 : MCInstPrinter(MAI, MII, MRI) {} 24 MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.h | 39 const MCRegisterInfo &MRI, 43 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.h | 27 const MCRegisterInfo &MRI) 28 : MCInstPrinter(MAI, MII, MRI) {} 25 SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.h | 35 const MCRegisterInfo &MRI, 39 const MCRegisterInfo &MRI,
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H A D | SparcMCTargetDesc.cpp | 37 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, argument 40 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 46 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, argument 49 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 147 const MCRegisterInfo &MRI, 149 return new SparcInstPrinter(MAI, MII, MRI); 143 createSparcMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.h | 27 const MCRegisterInfo &MRI) 28 : MCInstPrinter(MAI, MII, MRI) {} 26 XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 106 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 110 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); 118 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); 119 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); 181 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) argument 185 if (MRI->isPhysRegUsed(reg)) 189 if (MRI->isPhysRegUsed(reg)) 198 MachineRegisterInfo &MRI = MF.getRegInfo(); local 202 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed 203 || MRI 209 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.h | 68 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 78 const MCRegisterInfo &MRI, 82 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 84 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXFrameLowering.cpp | 40 MachineRegisterInfo &MRI = MF.getRegInfo(); local 45 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass); 52 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 63 MachineRegisterInfo *MRI; member in struct:__anon2316::A15SDOptimizer 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 164 MachineInstr *MI = MRI->getVRegDef(SReg); 230 for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg), 231 EE = MRI->use_end(); 263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 283 MRI->getRegClass(MI->getOperand(1).getReg()); 284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 315 MachineInstr *Def = MRI [all...] |