1249259Sdim//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief This file provides AMDGPU specific target descriptions. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#include "AMDGPUMCTargetDesc.h" 16249259Sdim#include "AMDGPUMCAsmInfo.h" 17249259Sdim#include "InstPrinter/AMDGPUInstPrinter.h" 18249259Sdim#include "llvm/MC/MCCodeGenInfo.h" 19249259Sdim#include "llvm/MC/MCInstrInfo.h" 20249259Sdim#include "llvm/MC/MCRegisterInfo.h" 21249259Sdim#include "llvm/MC/MCStreamer.h" 22249259Sdim#include "llvm/MC/MCSubtargetInfo.h" 23249259Sdim#include "llvm/MC/MachineLocation.h" 24249259Sdim#include "llvm/Support/ErrorHandling.h" 25249259Sdim#include "llvm/Support/TargetRegistry.h" 26249259Sdim 27249259Sdim#define GET_INSTRINFO_MC_DESC 28249259Sdim#include "AMDGPUGenInstrInfo.inc" 29249259Sdim 30249259Sdim#define GET_SUBTARGETINFO_MC_DESC 31249259Sdim#include "AMDGPUGenSubtargetInfo.inc" 32249259Sdim 33249259Sdim#define GET_REGINFO_MC_DESC 34249259Sdim#include "AMDGPUGenRegisterInfo.inc" 35249259Sdim 36249259Sdimusing namespace llvm; 37249259Sdim 38249259Sdimstatic MCInstrInfo *createAMDGPUMCInstrInfo() { 39249259Sdim MCInstrInfo *X = new MCInstrInfo(); 40249259Sdim InitAMDGPUMCInstrInfo(X); 41249259Sdim return X; 42249259Sdim} 43249259Sdim 44249259Sdimstatic MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { 45249259Sdim MCRegisterInfo *X = new MCRegisterInfo(); 46249259Sdim InitAMDGPUMCRegisterInfo(X, 0); 47249259Sdim return X; 48249259Sdim} 49249259Sdim 50249259Sdimstatic MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 51249259Sdim StringRef FS) { 52249259Sdim MCSubtargetInfo * X = new MCSubtargetInfo(); 53249259Sdim InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); 54249259Sdim return X; 55249259Sdim} 56249259Sdim 57249259Sdimstatic MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, 58249259Sdim CodeModel::Model CM, 59249259Sdim CodeGenOpt::Level OL) { 60249259Sdim MCCodeGenInfo *X = new MCCodeGenInfo(); 61249259Sdim X->InitMCCodeGenInfo(RM, CM, OL); 62249259Sdim return X; 63249259Sdim} 64249259Sdim 65249259Sdimstatic MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T, 66249259Sdim unsigned SyntaxVariant, 67249259Sdim const MCAsmInfo &MAI, 68249259Sdim const MCInstrInfo &MII, 69249259Sdim const MCRegisterInfo &MRI, 70249259Sdim const MCSubtargetInfo &STI) { 71249259Sdim return new AMDGPUInstPrinter(MAI, MII, MRI); 72249259Sdim} 73249259Sdim 74249259Sdimstatic MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 75249259Sdim const MCRegisterInfo &MRI, 76249259Sdim const MCSubtargetInfo &STI, 77249259Sdim MCContext &Ctx) { 78249259Sdim if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 79249259Sdim return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 80249259Sdim } else { 81252723Sdim return createR600MCCodeEmitter(MCII, MRI, STI); 82249259Sdim } 83249259Sdim} 84249259Sdim 85249259Sdimstatic MCStreamer *createMCStreamer(const Target &T, StringRef TT, 86249259Sdim MCContext &Ctx, MCAsmBackend &MAB, 87249259Sdim raw_ostream &_OS, 88249259Sdim MCCodeEmitter *_Emitter, 89249259Sdim bool RelaxAll, 90249259Sdim bool NoExecStack) { 91263509Sdim return createELFStreamer(Ctx, 0, MAB, _OS, _Emitter, false, false); 92249259Sdim} 93249259Sdim 94249259Sdimextern "C" void LLVMInitializeR600TargetMC() { 95249259Sdim 96249259Sdim RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget); 97249259Sdim 98249259Sdim TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo); 99249259Sdim 100249259Sdim TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo); 101249259Sdim 102249259Sdim TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo); 103249259Sdim 104249259Sdim TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo); 105249259Sdim 106249259Sdim TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter); 107249259Sdim 108249259Sdim TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter); 109249259Sdim 110249259Sdim TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend); 111249259Sdim 112249259Sdim TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer); 113249259Sdim} 114