Searched refs:MDT (Results 1 - 19 of 19) sorted by relevance

/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp109 MachineDominatorTree &MDT, bool IsPostRA);
116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
115 DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
128 VLIWPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
H A DUnreachableBlockElim.cpp124 MachineDominatorTree *MDT = getAnalysisIfAvailable<MachineDominatorTree>(); local
145 if (MDT && MDT->getNode(BB)) MDT->eraseNode(BB);
H A DLiveDebugVariables.cpp227 /// @param MDT Dominator tree.
231 LiveIntervals &LIS, MachineDominatorTree &MDT,
250 LiveIntervals &LIS, MachineDominatorTree &MDT,
286 MachineDominatorTree *MDT; member in class:__anon2131::LDVImpl
500 LiveIntervals &LIS, MachineDominatorTree &MDT,
549 MDT.getNode(MBB)->getChildren();
635 MachineDominatorTree &MDT,
651 extendDef(Idx, LocNo, 0, 0, 0, LIS, MDT, UVS);
664 extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS);
675 extendDef(Idx, LocNo, LR, VNI, 0, LIS, MDT, UV
497 extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
632 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
[all...]
H A DPostRASchedulerList.cpp138 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
204 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
208 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA),
265 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
298 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
203 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
H A DLiveRangeCalc.cpp23 MachineDominatorTree *MDT,
28 DomTree = MDT;
21 reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA) argument
H A DSplitKit.cpp332 MDT(mdt),
350 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
353 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
683 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
687 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
722 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
725 if (!IDom || !MDT.dominates(DefDomNode, IDom))
785 MDT.findNearestCommonDominator(Dom.first, ValMBB);
923 LRC.addLiveInBlock(LR, MDT[MBB], End);
926 LRC.addLiveInBlock(LR, MDT[MB
[all...]
H A DMachineBasicBlock.cpp894 if (MachineDominatorTree *MDT =
897 MachineDomTreeNode *SucccDTNode = MDT->getNode(Succ);
905 if (!MDT->dominates(SucccDTNode, MDT->getNode(PredBB))) {
912 MachineDomTreeNode *NewDTNode = MDT->addNewBlock(NMBB, this);
918 MDT->changeImmediateDominator(SucccDTNode, NewDTNode);
H A DSplitKit.h216 MachineDominatorTree &MDT; member in class:llvm::SplitEditor
H A DInlineSpiller.cpp62 MachineDominatorTree &MDT; member in class:__anon2127::InlineSpiller
147 MDT(pass.getAnalysis<MachineDominatorTree>()),
443 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
H A DMachineScheduler.cpp84 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
250 MDT = &getAnalysis<MachineDominatorTree>();
H A DScheduleDAGInstrs.cpp52 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h111 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
H A DMachineScheduler.h102 const MachineDominatorTree *MDT; member in struct:llvm::MachineSchedContext
332 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
H A DScheduleDAGInstrs.h79 const MachineDominatorTree &MDT; member in class:llvm::ScheduleDAGInstrs
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DR600Packetizer.cpp150 MachineDominatorTree &MDT)
151 : VLIWPacketizerList(MF, MLI, MDT, true),
328 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
331 R600PacketizerList Packetizer(Fn, MLI, MDT);
149 R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT) argument
H A DAMDILCFGStructurizer.cpp165 MDT = &getAnalysis<MachineDominatorTree>();
166 DEBUG(MDT->print(dbgs(), (const llvm::Module*)0););
177 MachineDominatorTree *MDT; member in class:__anon2445::AMDGPUCFGStructurizer
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp121 MachineDominatorTree &MDT,
186 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
188 : VLIWPacketizerList(MF, MLI, MDT, true){
195 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
199 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
185 HexagonPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT, const MachineBranchProbabilityInfo *MBPI) argument
H A DHexagonHardwareLoops.cpp66 MachineDominatorTree *MDT; member in struct:__anon2363::HexagonHardwareLoops
303 MDT = &getAnalysis<MachineDominatorTree>();
594 if (!MDT->properlyDominates(DefBB, Header))
601 if (!MDT->properlyDominates(DefBB, Header))
1049 if (!MDT->dominates(BBDef, Preheader))
1055 if (!MDT->properlyDominates(BBDef, L->getHeader()))
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp139 MachineDominatorTree *MDT; member in struct:__anon2425::PPCCTRLoopsVerify
631 MDT = &getAnalysis<MachineDominatorTree>();
638 if (!MDT->isReachableFromEntry(MBB))

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