Searched refs:InstrItins (Results 1 - 25 of 37) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h36 InstrItineraryData InstrItins; member in class:llvm::TargetSchedModel
77 return &InstrItins;
H A DDFAPacketizer.h46 const InstrItineraryData *InstrItins; member in class:llvm::DFAPacketizer
82 const InstrItineraryData *getInstrItins() const { return InstrItins; }
H A DResourcePriorityQueue.h63 const InstrItineraryData* InstrItins; member in class:llvm::ResourcePriorityQueue
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp36 return EnableSchedItins && !InstrItins.isEmpty();
60 STI->initInstrItins(InstrItins);
80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
170 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
179 // Rather than directly querying InstrItins stage latency, we call a TII
181 // applicable to the InstrItins model. InstrSchedModel should model all
235 return TII->getInstrLatency(&InstrItins, M
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H A DDFAPacketizer.cpp36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h41 InstrItineraryData InstrItins; member in class:llvm::HexagonSubtarget
48 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
H A DHexagonTargetMachine.h36 const InstrItineraryData* InstrItins; member in class:llvm::HexagonTargetMachine
55 return InstrItins;
H A DHexagonSubtarget.cpp73 InstrItins = getInstrItineraryForCPU(CPUString);
H A DHexagonTargetMachine.cpp80 InstrItins(&Subtarget.getInstrItineraryData()) {
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUSubtarget.h55 InstrItineraryData InstrItins; member in class:llvm::AMDGPUSubtarget
60 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
H A DAMDGPUTargetMachine.h36 const InstrItineraryData *InstrItins; member in class:llvm::AMDGPUTargetMachine
60 return InstrItins;
H A DAMDGPUSubtarget.cpp26 InstrItins = getInstrItineraryForCPU(CPU);
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.h38 InstrItineraryData InstrItins; member in class:llvm::PPCTargetMachine
64 return &InstrItins;
H A DPPCSubtarget.h67 InstrItineraryData InstrItins; member in class:llvm::PPCSubtarget
127 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
H A DPPCSubtarget.cpp111 InstrItins = getInstrItineraryForCPU(CPUName);
/freebsd-9.3-release/contrib/llvm/lib/MC/
H A DMCSubtargetInfo.cpp118 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
119 InstrItins =
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetMachine.h38 InstrItineraryData InstrItins; member in class:llvm::ARMBaseTargetMachine
54 return &InstrItins;
H A DARMSubtarget.h208 InstrItineraryData InstrItins; member in class:llvm::ARMSubtarget
351 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSubtarget.h119 InstrItineraryData InstrItins; member in class:llvm::MipsSubtarget
209 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
H A DMipsTargetMachine.h47 const InstrItineraryData &InstrItins; member in class:llvm::MipsTargetMachine
71 return Subtarget.inMips16Mode() ? 0 : &InstrItins;
H A DMipsSubtarget.cpp87 InstrItins = getInstrItineraryForCPU(CPUName);
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86TargetMachine.h35 InstrItineraryData InstrItins; member in class:llvm::X86TargetMachine
64 return &InstrItins;
H A DX86Subtarget.h199 InstrItineraryData InstrItins; member in class:llvm::X86Subtarget
405 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
/freebsd-9.3-release/contrib/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h137 void initInstrItins(InstrItineraryData &InstrItins) const;
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h40 const InstrItineraryData *InstrItins; member in class:llvm::ScheduleDAGSDNodes

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