Searched refs:ISD (Results 1 - 25 of 99) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp36 if (getOpcode() < ISD::BUILTIN_OP_END)
54 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
56 case ISD::PREFETCH: return "Prefetch";
57 case ISD::ATOMIC_FENCE: return "AtomicFence";
58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
59 case ISD::ATOMIC_SWAP: return "AtomicSwap";
60 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
61 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
62 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
63 case ISD
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H A DLegalizeVectorOps.cpp15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
154 if (Op.getOpcode() == ISD::LOAD) {
156 ISD::LoadExtType ExtType = LD->getExtensionType();
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
163 } else if (Op.getOpcode() == ISD::STORE) {
193 case ISD::ADD:
194 case ISD
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H A DLegalizeIntegerTypes.cpp50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD
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H A DLegalizeVectorTypes.cpp49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD
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H A DLegalizeDAG.cpp277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
415 Ptr = DAG.getNode(ISD
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H A DTargetLowering.cpp118 ISD::CondCode &CCCode,
126 case ISD::SETEQ:
127 case ISD::SETOEQ:
131 case ISD::SETNE:
132 case ISD::SETUNE:
136 case ISD::SETGE:
137 case ISD::SETOGE:
141 case ISD::SETLT:
142 case ISD::SETOLT:
146 case ISD
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H A DDAGCombiner.cpp172 ISD::NodeType ExtType);
270 SDValue N3, ISD::CondCode CC,
272 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
432 if (Op.getOpcode() == ISD::FNEG) return 2;
442 case ISD::ConstantFP:
446 case ISD::FADD:
452 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
462 case ISD::FSUB:
469 case ISD::FMUL:
470 case ISD
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/freebsd-9.3-release/contrib/llvm/include/llvm/Target/
H A DCostTable.h23 int ISD; member in struct:llvm::CostTblEntry
30 int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, argument
33 if (ISD == Tbl[i].ISD && Ty == Tbl[i].Type)
42 int CostTableLookup(const CostTblEntry<TypeTy>(&Tbl)[N], int ISD, member in namespace:llvm
44 return CostTableLookup(Tbl, N, ISD, Ty);
50 int ISD; member in struct:llvm::TypeConversionCostTblEntry
60 unsigned len, int ISD, CompareTy Dst,
63 if (ISD == Tbl[i].ISD
59 ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, CompareTy Dst, CompareTy Src) argument
74 int ISD, CompareTy Dst, CompareTy Src) { member in namespace:llvm
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/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp177 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
178 assert(ISD && "Invalid opcode");
183 { ISD::SHL, MVT::v4i32, 1 },
184 { ISD::SRL, MVT::v4i32, 1 },
185 { ISD::SRA, MVT::v4i32, 1 },
186 { ISD::SHL, MVT::v8i32, 1 },
187 { ISD::SRL, MVT::v8i32, 1 },
188 { ISD::SRA, MVT::v8i32, 1 },
189 { ISD::SHL, MVT::v2i64, 1 },
190 { ISD
358 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
467 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
622 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
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H A DX86CallingConv.h24 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
H A DX86ISelLowering.cpp74 if (Vec.getOpcode() == ISD::UNDEF)
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
123 if (Vec.getOpcode() == ISD::UNDEF)
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp184 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
185 assert(ISD && "Invalid opcode");
190 { ISD::FP_ROUND, MVT::v2f64, 2 },
191 { ISD::FP_EXTEND, MVT::v2f32, 2 },
192 { ISD::FP_EXTEND, MVT::v4f32, 4 }
195 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
196 ISD == ISD::FP_EXTEND)) {
198 int Idx = CostTableLookup(NEONFltDblTbl, ISD, L
397 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
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H A DARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DBasicTargetTransformInfo.cpp184 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
185 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
191 return TLI->isTypeLegal(VT) && TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
234 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
235 assert(ISD && "Invalid opcode");
244 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
254 if (!TLI->isOperationExpand(ISD, LT.second)) {
281 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
282 assert(ISD && "Invalid opcode");
305 if (TLI->isOperationLegalOrPromote(ISD, DstL
375 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
427 unsigned ISD = 0; local
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H A DTargetLoweringBase.cpp631 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
632 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
633 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
634 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
635 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
636 CCs[RTLIB::UNE_F32] = ISD::SETNE;
637 CCs[RTLIB::UNE_F64] = ISD::SETNE;
638 CCs[RTLIB::UNE_F128] = ISD::SETNE;
639 CCs[RTLIB::OGE_F32] = ISD
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H A DAnalysis.cpp146 /// getFCmpCondCode - Return the ISD condition code corresponding to
150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE;
153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ;
154 case FCmpInst::FCMP_OGT: return ISD::SETOGT;
155 case FCmpInst::FCMP_OGE: return ISD::SETOGE;
156 case FCmpInst::FCMP_OLT: return ISD::SETOLT;
157 case FCmpInst::FCMP_OLE: return ISD::SETOLE;
158 case FCmpInst::FCMP_ONE: return ISD::SETONE;
159 case FCmpInst::FCMP_ORD: return ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp34 ISD::ArgFlagsTy ArgFlags, CCState &State) {
50 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
54 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
55 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
56 setOperationAction(ISD::FPOW, MVT::f32, Legal);
57 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
58 setOperationAction(ISD::FABS, MVT::f32, Legal);
59 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
60 setOperationAction(ISD::FRINT, MVT::f32, Legal);
61 setOperationAction(ISD
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H A DAMDILISelLowering.cpp99 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
100 setOperationAction(ISD::SUBE, VT, Expand);
101 setOperationAction(ISD::SUBC, VT, Expand);
102 setOperationAction(ISD::ADDE, VT, Expand);
103 setOperationAction(ISD::ADDC, VT, Expand);
104 setOperationAction(ISD::BRCOND, VT, Custom);
105 setOperationAction(ISD::BR_JT, VT, Expand);
106 setOperationAction(ISD::BRIND, VT, Expand);
108 setOperationAction(ISD::SREM, VT, Expand);
109 setOperationAction(ISD
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H A DR600ISelLowering.cpp42 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
43 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
44 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
45 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
46 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
51 setCondCodeAction(ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp65 ISD::ArgFlagsTy ArgFlags, CCState &State);
70 ISD::ArgFlagsTy ArgFlags, CCState &State);
75 ISD::ArgFlagsTy ArgFlags, CCState &State);
80 ISD::ArgFlagsTy ArgFlags, CCState &State);
85 ISD::ArgFlagsTy ArgFlags, CCState &State);
90 ISD::ArgFlagsTy ArgFlags, CCState &State);
95 ISD::ArgFlagsTy ArgFlags, CCState &State) {
145 ISD::ArgFlagsTy ArgFlags, CCState &State) {
183 ISD::ArgFlagsTy ArgFlags, CCState &State) {
201 ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp81 setTargetDAGCombine(ISD::OR);
83 setTargetDAGCombine(ISD::AND);
84 setTargetDAGCombine(ISD::SRA);
85 setTargetDAGCombine(ISD::SRL);
86 setTargetDAGCombine(ISD::SHL);
88 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
89 setTargetDAGCombine(ISD::INTRINSIC_VOID);
90 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
126 if (N.getOpcode() == ISD::TargetConstant ||
127 N.getOpcode() == ISD::TargetGlobalAddress) {
282 if (N->getOpcode() != ISD::Constant)
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
371 if (Opcode == ISD::SHL) {
376 } else if (Opcode == ISD::SRL) {
383 } else if (Opcode == ISD::ROTL) {
421 if (Op0Opc == ISD
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h62 namespace ISD { namespace in namespace:llvm
74 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
79 /// and all operands of the specified node are ISD::UNDEF.
81 } // end llvm:ISD namespace
367 /// are the opcode values in the ISD and <target>ISD namespaces. For
372 /// \<target\>ISD namespace).
373 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
376 /// memory-referencing opcode (in the \<target\>ISD namespace and
379 return NodeType >= ISD
1883 namespace ISD { namespace
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
70 setOperationAction(ISD::ADD, VecTys[i], Legal);
71 setOperationAction(ISD::SUB, VecTys[i], Legal);
72 setOperationAction(ISD::LOAD, VecTys[i], Legal);
73 setOperationAction(ISD::STORE, VecTys[i], Legal);
74 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
77 setTargetDAGCombine(ISD
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