/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument 44 if (!SU || !SU->getInstr()) 49 switch (SU->getInstr()->getOpcode()) { 51 if (!ResourcesModel->canReserveResources(SU->getInstr())) 75 if (I->getSUnit() == SU) 83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument 86 if (!SU) { 92 // If this SU doe 220 releaseTopNode(SUnit *SU) argument 237 releaseBottomNode(SUnit *SU) argument 269 checkHazard(SUnit *SU) argument 280 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 321 bumpNode(SUnit *SU) argument 359 SUnit *SU = *(Pending.begin()+i); local 379 removeReady(SUnit *SU) argument 408 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P) argument 423 getSingleUnscheduledPred(SUnit *SU) argument 441 getSingleUnscheduledSucc(SUnit *SU) argument 466 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument 641 SUnit *SU; local 683 schedNode(SUnit *SU, bool IsTopNode) argument [all...] |
H A D | HexagonMachineScheduler.h | 88 bool isResourceAvailable(SUnit *SU); 89 bool reserveResources(SUnit *SU); 115 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate 123 SchedCandidate(): SU(NULL), SCost(0) {} 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 213 virtual void schedNode(SUnit *SU, bool IsTopNode); 215 virtual void releaseTopNode(SUnit *SU); [all...] |
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ResourcePriorityQueue.h | 88 void addNode(const SUnit *SU) { argument 92 void updateNode(const SUnit *SU) {} argument 108 /// Single cost function reflecting benefit of scheduling SU 110 signed SUSchedulingCost (SUnit *SU); 114 void initNumRegDefsLeft(SUnit *SU); 115 void updateNumRegDefsLeft(SUnit *SU); 116 signed regPressureDelta(SUnit *SU, bool RawPressure = false); 117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId); 125 virtual void remove(SUnit *SU); 131 bool isResourceAvailable(SUnit *SU); [all...] |
H A D | ScheduleDAGInstrs.h | 36 SUnit *SU; member in struct:llvm::VReg2SUnit 38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 48 SUnit *SU; member in struct:llvm::PhysRegSUOper 52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 164 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { 165 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) 166 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); 167 return SU->SchedClass; 222 virtual void dumpNode(const SUnit *SU) cons [all...] |
H A D | LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) { argument 61 void updateNode(const SUnit *SU) { argument 84 virtual void remove(SUnit *SU); 95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU); 96 SUnit *getSingleUnscheduledPred(SUnit *SU);
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H A D | MachineScheduler.h | 197 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 201 virtual void releaseTopNode(SUnit *SU) = 0; 204 virtual void releaseBottomNode(SUnit *SU) = 0; 225 // SU is in this queue if it's NodeQueueID is a superset of this ID. 226 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); } 242 iterator find(SUnit *SU) { argument 243 return std::find(Queue.begin(), Queue.end(), SU); 246 void push(SUnit *SU) { argument 247 Queue.push_back(SU); 402 getPressureDiff(const SUnit *SU) argument [all...] |
H A D | ScheduleDFS.h | 148 unsigned getNumInstrs(const SUnit *SU) const { 149 return DFSNodeData[SU->NodeNum].InstrCount; 161 ILPValue getILP(const SUnit *SU) const { 162 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth()); 172 unsigned getSubtreeID(const SUnit *SU) const { 175 assert(SU->NodeNum < DFSNodeData.size() && "New Node"); 176 return DFSNodeData[SU->NodeNum].SubtreeID;
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H A D | ScoreboardHazardRecognizer.h | 115 // Stalls provides an cycle offset at which SU will be scheduled. It will be 117 virtual HazardType getHazardType(SUnit *SU, int Stalls); 119 virtual void EmitInstruction(SUnit *SU);
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument 73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument 111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument 148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 156 static unsigned numberCtrlPredInSU(SUnit *SU) { argument 174 SUnit *SU = &(*SUnits)[i]; local 216 getSingleUnscheduledPred(SUnit *SU) argument 232 push(SUnit *SU) argument 247 isResourceAvailable(SUnit *SU) argument 290 reserveResources(SUnit *SU) argument 327 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument 361 regPressureDelta(SUnit *SU, bool RawPressure) argument 402 SUSchedulingCost(SUnit *SU) argument 472 scheduledNode(SUnit *SU) argument 548 initNumRegDefsLeft(SUnit *SU) argument 580 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument 633 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGVLIW.cpp | 86 void releaseSucc(SUnit *SU, const SDep &D); 87 void releaseSuccessors(SUnit *SU); 88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument 130 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 139 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument 141 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 releaseSucc(SU, *I); 153 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument [all...] |
H A D | ScheduleDAGRRList.cpp | 184 /// IsReachable - Checks if SU is reachable from TargetSU. 185 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument 186 return Topo.IsReachable(SU, TargetSU); 189 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 191 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument 192 return Topo.WillCreateCycle(SU, TargetSU); 195 /// AddPred - adds a predecessor edge to SUnit SU. 198 void AddPred(SUnit *SU, const SDep &D) { argument 199 Topo.AddPred(SU, D.getSUnit()); 200 SU 206 RemovePred(SUnit *SU, const SDep &D) argument 212 isReady(SUnit *SU) argument 364 ReleasePred(SUnit *SU, const SDep *PredEdge) argument 524 ReleasePredecessors(SUnit *SU) argument 621 AdvancePastStalls(SUnit *SU) argument 663 EmitNode(SUnit *SU) argument 705 ScheduleNodeBottomUp(SUnit *SU) argument 804 UnscheduleNodeBottomUp(SUnit *SU) argument 893 SUnit *SU = *I; local 903 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument 925 isOperandOf(const SUnit *SU, SDNode *N) argument 936 CopyAndMoveSuccessors(SUnit *SU) argument 1135 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument 1205 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument 1227 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument 1255 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument 1331 SUnit *SU = Interferences[i-1]; local 1502 SUnit *SU = PickNodeToScheduleBottomUp(); local 1706 remove(SUnit *SU) argument 1799 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); local [all...] |
H A D | ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back(); local 83 SU->SchedulingPref = Sched::None; 85 SU->SchedulingPref = TLI.getSchedulingPreference(N); 86 return SU; 90 SUnit *SU = newSUnit(Old->getNode()); local 91 SU->OrigNode = Old->OrigNode; 92 SU->Latency = Old->Latency; 93 SU->isVRegCycle = Old->isVRegCycle; 94 SU->isCall = Old->isCall; 95 SU [all...] |
H A D | ScheduleDAGSDNodes.h | 92 void InitVRegCycleFlag(SUnit *SU); 96 void InitNumRegDefsLeft(SUnit *SU); 100 virtual void computeLatency(SUnit *SU); 120 virtual void dumpNode(const SUnit *SU) const; 124 virtual std::string getGraphNodeLabel(const SUnit *SU) const; 140 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD); 180 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
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H A D | ScheduleDAGFast.cpp | 85 /// AddPred - adds a predecessor edge to SUnit SU. 87 void AddPred(SUnit *SU, const SDep &D) { argument 88 SU->addPred(D); 91 /// RemovePred - removes a predecessor edge from SUnit SU. 93 void RemovePred(SUnit *SU, const SDep &D) { argument 94 SU->removePred(D); 98 void ReleasePred(SUnit *SU, SDep *PredEdge); 99 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument 160 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument 182 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument 212 CopyAndMoveSuccessors(SUnit *SU) argument 387 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument 448 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument 469 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument [all...] |
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/ |
H A D | LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null. 55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument 57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 72 void LatencyPriorityQueue::push(SUnit *SU) { argument 76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 83 Queue.push_back(SU); 91 scheduledNode(SUnit *SU) argument 104 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument 133 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGInstrs.cpp | 198 /// the exit SU to the register defs and use list. This is because we want to 241 /// MO is an operand of SU's instruction that defines a physical register. Add 242 /// data dependencies from SU to any uses of the physical register. 243 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument 244 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 255 SUnit *UseSU = I->SU; 256 if (UseSU == SU) 265 Dep = SDep(SU, SDep::Artificial); 269 SU->hasPhysRegDefs = true; 270 Dep = SDep(SU, SDe 286 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument 365 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument 403 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument 609 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument 682 SUnit *SU = newSUnit(MI); local 760 SUnit *SU = MISUnitMap[MI]; local 1070 visitPreorder(const SUnit *SU) argument 1078 visitPostorderNode(const SUnit *SU) argument 1230 follow(const SUnit *SU) argument 1250 hasDataSucc(const SUnit *SU) argument 1268 const SUnit *SU = &*SI; local [all...] |
H A D | MachineScheduler.cpp | 392 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument 414 /// releaseSuccessors - Call releaseSucc on each of SU's successors. 415 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument 416 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 418 releaseSucc(SU, &*I); 426 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { argument 448 /// releasePredecessors - Call releasePred on each of SU's predecessors. 449 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { argument 450 for (SUnit::pred_iterator I = SU 571 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument 624 SUnit *SU = UI->SU; local 737 SUnit *SU = &(*I); local 875 scheduleMI(SUnit *SU, bool IsTopNode) argument 921 updateQueues(SUnit *SU, bool IsTopNode) argument 986 SUnit *SU; member in struct:__anon2146::LoadClusterMutation::LoadInfo 1020 SUnit *SU = Loads[Idx]; local 1068 SUnit *SU = &DAG->SUnits[Idx]; local 1118 SUnit *SU = &DAG->SUnits[--Idx]; local 1313 SUnit *SU = &DAG->SUnits[Idx]; local 1375 SUnit *SU; member in struct:__anon2149::GenericScheduler::SchedCandidate 1778 releaseTopNode(SUnit *SU) argument 1797 releaseBottomNode(SUnit *SU) argument 1885 checkHazard(SUnit *SU) argument 2008 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 2103 bumpNode(SUnit *SU) argument 2216 SUnit *SU = *(Pending.begin()+i); local 2237 removeReady(SUnit *SU) argument 2378 getWeakLeft(const SUnit *SU, bool isTop) argument 2389 biasPhysRegCopy(const SUnit *SU, bool isTop) argument 2746 SUnit *SU; local 2786 reschedulePhysRegCopies(SUnit *SU, bool isTop) argument 2817 schedNode(SUnit *SU, bool IsTopNode) argument 2919 SUnit *SU = ReadyQ.back(); local 2938 schedNode(SUnit *SU, bool IsTopNode) argument 2944 releaseBottomNode(SUnit *SU) argument 3006 SUnit *SU; local 3028 schedNode(SUnit *SU, bool IsTopNode) argument 3030 releaseTopNode(SUnit *SU) argument 3033 releaseBottomNode(SUnit *SU) argument 3095 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument 3105 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument [all...] |
H A D | ScheduleDAG.cpp | 183 SUnit *SU = WorkList.pop_back_val(); 184 SU->isDepthCurrent = false; 185 for (SUnit::const_succ_iterator I = SU->Succs.begin(), 186 E = SU->Succs.end(); I != E; ++I) { 199 SUnit *SU = WorkList.pop_back_val(); 200 SU->isHeightCurrent = false; 201 for (SUnit::const_pred_iterator I = SU->Preds.begin(), 202 E = SU->Preds.end(); I != E; ++I) { 317 dbgs() << "SU(" << NodeNum << "): "; 346 dbgs() << "SU(" << [all...] |
H A D | ScoreboardHazardRecognizer.cpp | 118 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 165 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); 166 DEBUG(DAG->dumpNode(SU)); 178 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument 184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 59 SUnit *SU = 0; local 95 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 98 SU = pickAlu(); 99 if (!SU && !PhysicalRegCopy.empty()) { 100 SU = PhysicalRegCopy.front(); 103 if (SU) { 110 if (!SU) { 112 SU = pickOther(IDFetch); 113 if (SU) 118 if (!SU) { 141 schedNode(SUnit *SU, bool IsTopNode) argument 189 releaseTopNode(SUnit *SU) argument 193 releaseBottomNode(SUnit *SU) argument 293 getInstKind(SUnit* SU) argument 322 SUnit *SU = *It; local 432 SUnit *SU = AttemptFillSlot(3, true); local 441 SUnit *SU = AttemptFillSlot(Chan, false); local 455 SUnit *SU = 0; local [all...] |
H A D | R600MachineScheduler.h | 79 virtual void schedNode(SUnit *SU, bool IsTopNode); 80 virtual void releaseTopNode(SUnit *SU); 81 virtual void releaseBottomNode(SUnit *SU); 87 int getInstKind(SUnit *SU); 89 AluKind getAluKind(SUnit *SU) const;
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 38 MachineInstr *MI = SU->getInstr(); 76 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 85 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument 86 MachineInstr *MI = SU->getInstr(); 92 ScoreboardHazardRecognizer::EmitInstruction(SU);
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H A D | ARMHazardRecognizer.h | 40 virtual HazardType getHazardType(SUnit *SU, int Stalls); 42 virtual void EmitInstruction(SUnit *SU);
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU); 68 virtual HazardType getHazardType(SUnit *SU, int Stalls); 69 virtual void EmitInstruction(SUnit *SU);
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H A D | PPCHazardRecognizers.cpp | 26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 32 ScoreboardHazardRecognizer::EmitInstruction(SU); 36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 137 getHazardType(SUnit *SU, int Stalls) { argument 140 MachineInstr *MI = SU->getInstr(); 197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { argument 198 MachineInstr *MI = SU->getInstr();
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