Searched refs:v32i16 (Results 1 - 12 of 12) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp371 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
372 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
373 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
374 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
394 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence
395 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence
396 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence
397 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence
483 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
484 { ISD::SRL, MVT::v32i16,
1386 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, member in class:MVT
1387 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, member in class:MVT
1399 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, member in class:MVT
1412 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, member in class:MVT
1415 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, member in class:MVT
1426 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, member in class:MVT
[all...]
H A DX86ISelDAGToDAG.cpp851 // Emulate v32i16/v64i8 broadcast without BWI.
852 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
853 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8;
860 unsigned Index = VT == MVT::v32i16 ? 16 : 32;
875 // Emulate v32i16/v64i8 broadcast without BWI.
876 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
877 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8;
888 unsigned Index = VT == MVT::v32i16 ? 16 : 32;
4103 VPTESTM_CASE(v32i16, WZ##SUFFIX)
H A DX86ISelLowering.cpp1463 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1473 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1518 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1535 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1538 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1541 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1567 for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1572 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom);
1573 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1579 setOperationAction(ISD::MUL, MVT::v32i16, HasBW
[all...]
H A DX86FastISel.cpp455 case MVT::v32i16:
627 case MVT::v32i16:
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h89 v32i16 = 41, // 32 x i16
394 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
497 case v32i16:
630 case v32i16:
878 case v32i16:
1048 if (NumElements == 32) return MVT::v32i16;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp249 case MVT::v32i16:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp106 case MVT::v32i16: return "MVT::v32i16";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp17 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
27 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
207 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32})
210 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32})
H A DHexagonISelDAGToDAG.cpp109 case MVT::v32i16:
499 case MVT::v32i16:
H A DHexagonInstrInfo.cpp2688 case MVT::v32i16:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp114 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom);
H A DSIISelLowering.cpp212 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
222 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);

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