Searched refs:isReg (Results 1 - 25 of 347) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp31 static bool isReg(const MCInst &MI, unsigned OpNo) { function
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
128 if (Op.isReg()) {
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
241 return isReg<Mip
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h220 return isReg() ? 0 : SubReg_TargetFlags;
223 assert(!isReg() && "Register operands can't have target flags");
228 assert(!isReg() && "Register operands can't have target flags");
318 /// isReg - Tests if this is a MO_Register operand.
319 bool isReg() const { return OpKind == MO_Register; } function
359 assert(isReg() && "This is not a register operand!");
364 assert(isReg() && "Wrong MachineOperand accessor");
369 assert(isReg() && "Wrong MachineOperand accessor");
374 assert(isReg() && "Wrong MachineOperand accessor");
379 assert(isReg()
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H A DLiveRegUnits.h54 if (!O->isReg())
170 return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXProxyRegErasure.cpp99 assert(InOp.isReg() && "ProxyReg input operand should be a register.");
100 assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
113 if (Op.isReg() && Op.getReg() == From.getReg()) {
H A DNVPTXPeephole.cpp84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMachineLocation.h46 bool isReg() const { return IsRegister; } function
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp45 if (MI.getOperand(i).isReg() &&
50 if (MI.getOperand(i).isReg() &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelector.cpp51 if (MO.isReg() && MO.getReg())
59 if (!Root.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp112 if (MCOp.isReg())
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
154 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
193 assert(Op1.isReg() && "First operand is not register.");
225 assert(Op1.isReg() && "First operand is not register.");
227 assert(Op2.isReg() && "Second operand is not register.");
264 assert(Op1.isReg() && "First operand is not register.");
292 if (MCOp.isReg() || MCO
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp68 if (Src.isReg() &&
84 if (Dst.isReg() &&
86 MI.getOperand(1).isReg())
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
130 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
394 if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
396 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
H A DSIFoldOperands.cpp53 assert(FoldOp->isReg() || FoldOp->isGlobal());
66 bool isReg() const { function in struct:__anon3971::FoldCandidate
190 assert(Old.isReg());
393 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
394 !MI->getOperand(CommuteIdx1).isReg()))
412 if (!OtherOp.isReg() ||
483 assert (Sub->isReg());
486 SubDef && Sub->isReg() && !Sub->getSubReg() &&
495 if (!Op->isReg())
527 if (!OpToFold.isReg())
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H A DSIOptimizeExecMaskingPreRA.cpp118 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
140 if (Op1->isImm() && Op2->isReg())
142 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
157 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
270 if (Op.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp82 if (MO.isReg() && MO.getReg().isValid() &&
109 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) {
127 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp72 if (!Op1.isReg() || !Op2.isReg())
91 if (!RA.isReg())
100 if (!RT.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
110 RI->getOperand(1).isReg() &&
115 RI->getOperand(0).isReg() &&
117 RI->getOperand(1).isReg() &&
207 if (!MO.isReg() || !(Reg = MO.getReg()))
236 if (!MO.isReg() || !(Reg = MO.getReg()))
H A DLanaiMemAluCombiner.cpp185 return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
247 assert((AluOffset.isReg() || AluOffset.isImm()) &&
264 if (AluOffset.isReg())
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0)
318 } else if (Op2.isReg()) {
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
356 if (Offset->isReg() && InstrUsesReg(First, Offset))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
61 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
74 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
87 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
99 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
112 if (MO.isReg() || MO.isImm())
126 assert(MI.getOperand(OpNo+1).isReg());
144 assert(MI.getOperand(OpNo+1).isReg());
162 assert(MI.getOperand(OpNo+1).isReg());
269 assert(MI.getOperand(OpNo + 1).isReg()
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
119 assert(MO.isReg());
140 assert(RegOp.isReg() && "Expected register operand");
254 if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp127 if (MO.isReg())
154 if (MO.isReg() || MO.isImm())
189 if (MO.isReg() || MO.isImm())
202 if (MO.isReg() || MO.isImm())
215 if (MO.isReg() || MO.isImm())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDeadMachineInstructionElim.cpp78 if (MO.isReg() && MO.isDef()) {
152 if (MO.isReg() && MO.isDef()) {
171 if (MO.isReg() && MO.isUse()) {
H A DMIRCanonicalizerPass.cpp167 if (!MO.isReg())
187 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
199 if (II->getOperand(i).isReg()) {
315 if (!MI->getOperand(0).isReg())
317 if (!MI->getOperand(1).isReg())
355 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp91 if (MO.isReg()) {
146 assert(MO.isReg() && "printAtomicMemOp can only print register operands");
169 assert(MO.isReg() && "printVMaskReg can only print register operands");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp55 if (Op.isReg()) {
71 assert(RegOp.isReg() && "Register operand not a register");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp321 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
374 if (!Op.isReg() || !Op.isDef())
499 if (!Op.isReg() || !DefRegs.count(Op))
582 if (SO.isReg()) {
642 if (SrcOp.isReg()) {
681 if (Op.isReg())
690 if (ST.isReg() && SF.isReg()) {
730 if (!Op.isReg() || !Op.isDef())
766 if (!Op.isReg() || !O
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H A DHexagonHardwareLoops.cpp341 bool isReg() const { return Kind == CV_Register; } function in class:__anon4129::CountValue
345 assert(isReg() && "Wrong CountValue accessor");
350 assert(isReg() && "Wrong CountValue accessor");
360 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
677 if (Op1.isReg()) {
697 if (InitialValue->isReg()) {
707 if (EndValue->isReg()) {
737 if (Start->isReg()) {
743 if (End->isReg()) {
750 if (!Start->isReg()
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