| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 107 Register ZeroReg = MRI->createVirtualRegister(RC); local
112 ZeroReg);
118 .addReg(ZeroReg)
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| H A D | X86FrameLowering.cpp | 791 // ZeroReg = 0
794 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
834 ZeroReg = InProlog ? X86::RCX
894 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
895 .addReg(ZeroReg, RegState::Undef)
896 .addReg(ZeroReg, RegState::Undef);
903 .addReg(ZeroReg)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
182 if (ZeroReg)
183 MIB.addReg(ZeroReg);
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| H A D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; local
93 ZeroReg = Mips::ZERO;
99 ZeroReg = Mips::ZERO_64;
105 // Replace uses with ZeroReg.
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
122 MO.setReg(ZeroReg);
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| H A D | MipsAsmPrinter.cpp | 144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; local
145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); local
553 putConstant(I, ZeroReg, 0);
558 ZeroReg))
564 RHSReg, ZeroReg))
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| H A D | ARMFastISel.cpp | 1476 unsigned ZeroReg = fastMaterializeConstant(Zero); local
1479 .addReg(ZeroReg).addImm(1)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2645 unsigned Opcode, unsigned ZeroReg,
2660 MIB.addReg(ZeroReg);
3901 unsigned CombineOpc, unsigned ZeroReg = 0,
3920 if (MI->getOperand(3).getReg() != ZeroReg)
3930 unsigned MulOpc, unsigned ZeroReg) {
3931 return canCombine(MBB, MO, MulOpc, ZeroReg, true);
3991 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
3993 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
4646 unsigned BitSize, OrrOpc, ZeroReg;
4651 ZeroReg
2641 copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef<unsigned> Indices) const argument
[all...] |
| H A D | AArch64ExpandPseudoInsts.cpp | 75 unsigned ExtendImm, unsigned ZeroReg,
181 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
214 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
179 expandCMP_SWAP( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp, unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, MachineBasicBlock::iterator &NextMBBI) argument
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| H A D | AArch64InstrInfo.h | 151 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
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| H A D | AArch64FastISel.cpp | 390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
393 ResultReg).addReg(ZeroReg, getKillRegState(true));
4978 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; local
4981 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
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| H A D | AArch64ISelDAGToDAG.cpp | 2788 unsigned ZeroReg; local
2792 ZeroReg = AArch64::WZR;
2796 ZeroReg = AArch64::XZR;
2799 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT);
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| H A D | AArch64ISelLowering.cpp | 12454 unsigned ZeroReg; local
12457 ZeroReg = AArch64::WZR;
12460 ZeroReg = AArch64::XZR;
12464 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | InstructionSelectorImpl.h | 816 int64_t ZeroReg = MatchTable[CurrentIdx++]; local
820 OutMIs[NewInsnID].addReg(ZeroReg);
826 << OpIdx << ", " << ZeroReg << ")\n"); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2721 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); local
2741 SrcReg = ZeroReg;
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2787 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2816 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
4189 unsigned ZeroReg; local
4194 ZeroReg = Mips::ZERO_64;
4198 ZeroReg = Mips::ZERO;
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg,
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1612 MCRegister ZeroReg;
1615 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1617 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1621 UseMI.getOperand(UseIdx).setReg(ZeroReg); variable
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| H A D | PPCISelLowering.cpp | 11464 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
11533 if (ptrA != ZeroReg) {
11578 .addReg(ZeroReg)
11622 .addReg(ZeroReg)
12515 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; local
12548 if (ptrA != ZeroReg) {
12605 .addReg(ZeroReg)
12629 .addReg(ZeroReg)
12642 .addReg(ZeroReg)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6632 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); local
6634 ZeroReg, 0);
6635 HeaderPHIBuilder.addReg(ZeroReg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2402 Register ZeroReg = Zero.getReg(0); local
2403 MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
|