Lines Matching refs:ZeroReg
2645 unsigned Opcode, unsigned ZeroReg,
2660 MIB.addReg(ZeroReg);
3901 unsigned CombineOpc, unsigned ZeroReg = 0,
3920 if (MI->getOperand(3).getReg() != ZeroReg)
3930 unsigned MulOpc, unsigned ZeroReg) {
3931 return canCombine(MBB, MO, MulOpc, ZeroReg, true);
3991 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
3993 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
4646 unsigned BitSize, OrrOpc, ZeroReg;
4651 ZeroReg = AArch64::WZR;
4658 ZeroReg = AArch64::XZR;
4674 .addReg(ZeroReg)
4690 unsigned SubOpc, ZeroReg;
4694 ZeroReg = AArch64::WZR;
4700 ZeroReg = AArch64::XZR;
4708 .addReg(ZeroReg)
4738 unsigned BitSize, OrrOpc, ZeroReg;
4743 ZeroReg = AArch64::WZR;
4750 ZeroReg = AArch64::XZR;
4765 .addReg(ZeroReg)