Searched refs:WRITE_REG32 (Results 1 - 12 of 12) sorted by relevance
| /freebsd-13-stable/sys/dev/qlxge/ |
| H A D | qls_hw.c | 265 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
266 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
275 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
276 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
285 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
291 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value);
330 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
331 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
341 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
342 WRITE_REG32(h
[all...] |
| H A D | qls_dump.c | 406 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);
430 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
432 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);
612 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \
816 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
828 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
852 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
868 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));
1221 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1234 WRITE_REG32(h
[all...] |
| H A D | qls_isr.c | 349 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);
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| H A D | qls_hw.h | 905 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) macro
912 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx))
919 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
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| /freebsd-13-stable/sys/dev/qlxgb/ |
| H A D | qla_hw.h | 797 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\
801 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val)
804 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\
809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\
811 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\
818 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\
825 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
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| H A D | qla_reg.h | 233 #define WRITE_REG32(ha, reg, val) \ macro
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| /freebsd-13-stable/sys/dev/qlxgbe/ |
| H A D | ql_inline.h | 66 WRITE_REG32(ha, id_reg, id_val);
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| H A D | ql_misc.c | 72 WRITE_REG32(ha, wnd_reg, addr);
89 WRITE_REG32(ha, Q8_WILD_CARD, *val);
1309 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
1317 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
1389 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
1397 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
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| H A D | ql_isr.c | 793 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
909 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
910 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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| H A D | ql_ioctl.c | 120 WRITE_REG32(ha, u.rv->reg, u.rv->val);
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| H A D | ql_hw.h | 207 #define WRITE_REG32(ha, reg, val) \ macro
1721 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
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| H A D | ql_hw.c | 1436 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
1440 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
1482 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
1483 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2884 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
2885 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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Completed in 178 milliseconds