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  • only in /freebsd-13-stable/sys/dev/qlxge/

Lines Matching refs:WRITE_REG32

265 	WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
266 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
275 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
276 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
285 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
291 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value);
330 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
331 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
341 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
342 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
385 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index);
386 WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data);
798 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
801 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
837 WRITE_REG32(ha, Q81_CTL_SYSTEM, value);
841 WRITE_REG32(ha, Q81_CTL_NIC_RCV_CONFIG, value);
856 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, value);
862 WRITE_REG32(ha, Q81_CTL_INTR_MASK, value);
909 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
915 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
1024 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1027 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1034 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1103 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1106 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1113 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1173 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
1176 WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
1183 WRITE_REG32(ha, Q81_CTL_CONFIG, value);
1792 WRITE_REG32(ha, Q81_CTL_FLASH_ADDR, (addr | Q81_CTL_FLASH_ADDR_R));
1888 WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value));
1905 WRITE_REG32(ha, Q81_CTL_SEMAPHORE, mask);
1947 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
1972 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
1976 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
1995 WRITE_REG32(ha, Q81_CTL_RESET, data);
2173 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_SET_HTR_INTR);
2211 WRITE_REG32(ha,\
2231 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
2391 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
2398 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\