Searched refs:VectorSize (Results 1 - 10 of 10) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULibFunc.cpp385 P.ArgType = AMDGPULibFunc::I32; P.VectorSize = 4; break;
387 P.ArgType = AMDGPULibFunc::U32; P.VectorSize = 4; break;
389 P.ArgType = AMDGPULibFunc::F32; P.VectorSize = 4; break;
408 P.VectorSize = 2; P.PtrKind = AMDGPULibFunc::BYVALUE; break;
410 P.VectorSize = 3; P.PtrKind = AMDGPULibFunc::BYVALUE; break;
412 P.VectorSize = 4; P.PtrKind = AMDGPULibFunc::BYVALUE; break;
414 P.VectorSize = 8; P.PtrKind = AMDGPULibFunc::BYVALUE; break;
416 P.VectorSize = 16; P.PtrKind = AMDGPULibFunc::BYVALUE; break;
433 case AMDGPULibFunc::IMG1DA: P.VectorSize = 2; break;
434 case AMDGPULibFunc::IMG1DB: P.VectorSize
[all...]
H A DAMDGPULibFunc.h293 unsigned char VectorSize; member in struct:llvm::AMDGPULibFuncBase::Param
300 VectorSize = 1;
H A DAMDGPULibCalls.cpp468 return FInfo.getLeads()[0].VectorSize;
518 nf.getLeads()[0].VectorSize = FInfo.getLeads()[0].VectorSize;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp247 unsigned VectorSize, MCContext &Ctx) {
258 auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; local
638 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
648 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
656 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
664 MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
679 MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
694 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
711 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContex
246 ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx) argument
[all...]
H A DHexagonInstrInfo.cpp2728 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); local
2729 assert(isPowerOf2_32(VectorSize));
2730 if (Offset & (VectorSize-1))
2732 return isInt<4>(Offset >> Log2_32(VectorSize));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp437 // VectorSize = 128 => Lane = 1
438 // VectorSize = 256 => Lane = 2
443 int VectorSize = VT.getSizeInBits(); local
445 int LaneCount = std::max(VectorSize / 128, 1);
456 int VectorSize = VT.getSizeInBits(); local
457 int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1);
/freebsd-13-stable/contrib/llvm-project/clang/utils/TableGen/
H A DNeonEmitter.cpp1598 int64_t VectorSize = cast<IntInit>(Expr->getArg(0))->getValue();
1599 VectorSize /= ElementSize;
1602 for (unsigned VI = 0; VI < Elts2.size(); VI += VectorSize) {
1603 for (int LI = VectorSize - 1; LI >= 0; --LI) {
/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaDeclAttr.cpp4038 llvm::APInt VectorSize(64, 0);
4047 !Str.substr(1, VectorStringLength).getAsInteger(10, VectorSize) &&
4048 VectorSize.isPowerOf2()) {
4055 VectorSize = 0;
4059 if (!VectorSize)
4099 VectorSize.getBoolValue()) {
4139 if (VectorSize.getBoolValue()) {
4140 NewTy = Context.getVectorType(NewTy, VectorSize.getZExtValue(),
H A DTreeTransform.h13968 IntegerLiteral *VectorSize local
13971 return SemaRef.BuildExtVectorType(ElementType, VectorSize, AttributeLoc);
/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp5498 int VectorSize = 0;
5500 VectorSize = 64;
5502 VectorSize = 128;
5510 Ty, VectorSize ? VectorSize / Ty->getPrimitiveSizeInBits() : 1);
5517 int Elts = VectorSize ? VectorSize / ArgType->getPrimitiveSizeInBits() : 1;

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