Searched refs:VecSrc (Results 1 - 4 of 4) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp1072 Value *VecSrc; local
1073 if (match(VecOp, m_BitCast(m_Value(VecSrc))) &&
1076 VecSrc->getType()->isVectorTy() && !ScalarSrc->getType()->isVectorTy() &&
1077 cast<VectorType>(VecSrc->getType())->getElementType() ==
1079 // inselt (bitcast VecSrc), (bitcast ScalarSrc), IdxOp -->
1080 // bitcast (inselt VecSrc, ScalarSrc, IdxOp)
1081 Value *NewInsElt = Builder.CreateInsertElement(VecSrc, ScalarSrc, IdxOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1136 Value *VecSrc = CI.getOperand(2); local
1138 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
1163 Value *VecSrc = CI.getOperand(2); local
1165 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
1234 Value *VecSrc = NumArgs == 5 ? CI.getArgOperand(3) : local
1238 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2143 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); local
2147 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp11405 SDValue VecSrc = N0.getOperand(0); local
11406 EVT VecSrcVT = VecSrc.getValueType();
11413 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, VecSrc,

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