Searched refs:ShOp (Results 1 - 6 of 6) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
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| H A D | ARMMCCodeEmitter.cpp | 1252 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1253 unsigned SBits = getShiftOp(ShOp);
1290 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1292 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2002 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, argument
2005 Op->ShiftExtend.Type = ShOp;
2762 AArch64_AM::ShiftExtendType ShOp = local
2779 if (ShOp == AArch64_AM::InvalidShiftExtend)
2788 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
2789 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
2790 ShOp == AArch64_AM::MSL) {
2799 AArch64Operand::CreateShiftExtend(ShOp,
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3446 SDValue ShOp = N->getOperand(1); local
3447 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3453 SDValue ShOp = N->getOperand(1); local
3455 EVT ShVT = ShOp.getValueType();
3457 ShOp = GetWidenedVector(ShOp);
3458 ShVT = ShOp.getValueType();
3464 ShOp = ModifyToType(ShOp, ShWidenVT);
3466 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
[all...] |
| H A D | DAGCombiner.cpp | 4590 SDValue ShOp = N0.getOperand(1);
4591 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4592 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4595 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4598 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4603 ShOp = N0.getOperand(0);
4604 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4605 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4608 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4611 return DAG.getVectorShuffle(VT, DL, ShOp, Logi
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1958 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; local
1961 ShOp = ARM_AM::lsl;
1964 ShOp = ARM_AM::lsr;
1967 ShOp = ARM_AM::asr;
1970 ShOp = ARM_AM::ror;
1974 if (ShOp == ARM_AM::ror && imm == 0)
1975 ShOp = ARM_AM::rrx;
1983 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1985 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
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