Searched refs:SchedClass (Results 1 - 14 of 14) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp57 unsigned SchedClass) const {
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); local
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
78 SCDesc = getSchedClassDesc(SchedClass);
81 if (SchedClass)
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); local
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
134 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h19 inline bool is_TC1(unsigned SchedClass) { argument
20 switch (SchedClass) {
66 inline bool is_TC2(unsigned SchedClass) { argument
67 switch (SchedClass) {
98 inline bool is_TC3x(unsigned SchedClass) { argument
99 switch (SchedClass) {
129 inline bool is_TC2early(unsigned SchedClass) { argument
130 switch (SchedClass) {
139 inline bool is_TC4x(unsigned SchedClass) { argument
140 switch (SchedClass) {
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H A DHexagonInstrInfo.cpp2181 unsigned SchedClass = MI.getDesc().getSchedClass(); local
2182 return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2373 unsigned SchedClass = MI.getDesc().getSchedClass(); local
2374 return !is_TC1(SchedClass);
2622 unsigned SchedClass = MI.getDesc().getSchedClass(); local
2623 return is_TC1(SchedClass);
2627 unsigned SchedClass = MI.getDesc().getSchedClass(); local
2628 return is_TC2(SchedClass);
2632 unsigned SchedClass local
2637 unsigned SchedClass = MI.getDesc().getSchedClass(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel())
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr());
124 return SU->SchedClass;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp135 unsigned SchedClass = MI->getDesc().getSchedClass(); local
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
146 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
147 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
327 unsigned SchedClass = MI->getDesc().getSchedClass(); local
328 return MCSchedModel::getReciprocalThroughput(SchedClass,
340 unsigned SchedClass = TII->get(Opcode).getSchedClass(); local
342 return MCSchedModel::getReciprocalThroughput(SchedClass,
345 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
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H A DMachinePipeliner.cpp991 unsigned SchedClass = Inst->getDesc().getSchedClass(); local
995 make_range(InstrItins->beginStage(SchedClass),
996 InstrItins->endStage(SchedClass))) {
1008 STI->getSchedModel().getSchedClassDesc(SchedClass);
1038 unsigned SchedClass = MI.getDesc().getSchedClass(); local
1041 make_range(InstrItins->beginStage(SchedClass),
1042 InstrItins->endStage(SchedClass))) {
1051 STI->getSchedModel().getSchedClassDesc(SchedClass);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h266 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
267 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
268 return SU->SchedClass;
H A DTargetSubtargetInfo.h136 /// Resolve a SchedClass at runtime, where SchedClass identifies an
138 /// another variant SchedClass, but repeated invocation must quickly terminate
139 /// in a nonvariant SchedClass.
140 virtual unsigned resolveSchedClass(unsigned SchedClass, argument
H A DScheduleDAG.h253 const MCSchedClassDesc *SchedClass = variable
254 nullptr; ///< nullptr or resolved SchedClass.
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h193 unsigned short SchedClass; // enum identifying instr sched class member in class:llvm::MCInstrDesc
604 unsigned getSchedClass() const { return SchedClass; }
H A DMCSchedule.h367 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
H A DMCSubtargetInfo.h214 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp428 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); local
429 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
435 unsigned Stage = II[SchedClass].LastStage - 1;
447 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); local
448 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
458 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); local
464 for (unsigned Stage = II[SchedClass].FirstStage + 1;
465 Stage < II[SchedClass].LastStage; ++Stage) {
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp44 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
981 // Generate the SchedClass table for this processor and update global
1004 // A Variant SchedClass has no resources of its own.
1019 // Determine if the SchedClass is actually reachable on this processor. If
1150 // Create an entry for each operand Read in this SchedClass.
1187 // Add the information for this SchedClass to the global tables using basic
1244 // Emit SchedClass tables for all processors and associated global tables.
1296 // Emit a SchedClass table for each processor.
1320 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); local
1321 OS << " {DBGFIELD(\"" << SchedClass
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