Lines Matching refs:SchedClass
44 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
981 // Generate the SchedClass table for this processor and update global
1004 // A Variant SchedClass has no resources of its own.
1019 // Determine if the SchedClass is actually reachable on this processor. If
1150 // Create an entry for each operand Read in this SchedClass.
1187 // Add the information for this SchedClass to the global tables using basic
1244 // Emit SchedClass tables for all processors and associated global tables.
1296 // Emit a SchedClass table for each processor.
1320 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1321 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1322 if (SchedClass.Name.size() < 18)
1323 OS.indent(18 - SchedClass.Name.size());
1514 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
1575 OS << " switch (SchedClass) {\n";
1636 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1648 << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
1651 << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);\n"
1729 << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
1746 << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
1749 << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); \n";
1864 << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
1871 << " unsigned resolveSchedClass(unsigned SchedClass, "
1874 << " unsigned resolveVariantSchedClass(unsigned SchedClass,"