Searched refs:SDWA (Results 1 - 9 of 9) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp1 //===- SIPeepholeSDWA.cpp - Peephole optimization for SDWA instructions ---===//
9 /// \file This pass tries to apply several peephole SDWA patterns.
59 STATISTIC(NumSDWAPatternsFound, "Number of SDWA patterns found.");
61 "Number of instruction converted to SDWA.");
99 StringRef getPassName() const override { return "SI Peephole SDWA"; }
138 using namespace AMDGPU::SDWA;
213 INITIALIZE_PASS(SIPeepholeSDWA, DEBUG_TYPE, "SI Peephole SDWA", false, false)
249 OS << "SDWA src: " << *getTargetOperand()
257 OS << "SDWA dst: " << *getTargetOperand()
264 OS << "SDWA preserv
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H A DSIDefines.h41 SDWA = 1 << 14,
169 // Operand for SDWA instructions
230 SDWA = 2,
435 namespace SDWA { namespace in namespace:llvm::SIInstrFlags::SISrcMods::SIOutMods::AMDGPU::VGPRIndexMode::AMDGPUAsmVariants::AMDGPU::AMDGPU::SendMsg::Hwreg::Swizzle
468 } // namespace SDWA
H A DAMDGPUInstructionSelector.cpp1755 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel
1756 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused
1757 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel
2641 assert(STI.hasSDWA() && "no target has VOP3P but not SDWA");
2704 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel
2705 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused
2706 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel
2722 .addImm(AMDGPU::SDWA::WORD_0) // $dst_sel
2723 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused
2724 .addImm(AMDGPU::SDWA
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H A DSIInstrInfo.h436 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
440 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
H A DSIInstrInfo.cpp782 .addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0
783 : AMDGPU::SDWA::SdwaSel::WORD_1)
784 .addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE)
785 .addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0
786 : AMDGPU::SDWA::SdwaSel::WORD_1)
3614 // Verify SDWA
3617 ErrInfo = "SDWA is not supported on this target";
3633 ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
3639 ErrInfo = "Only reg allowed as operands in SDWA instructions on GFX9";
3650 ErrInfo = "OMod not allowed in SDWA instruction
6829 SDWA = 2, enumerator in enum:SIEncodingFamily
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp387 using namespace AMDGPU::SDWA;
417 using namespace AMDGPU::SDWA;
H A DAMDGPUInstPrinter.cpp342 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
869 using namespace llvm::AMDGPU::SDWA;
880 default: llvm_unreachable("Invalid SDWA data select operand");
908 using namespace llvm::AMDGPU::SDWA;
916 default: llvm_unreachable("Invalid SDWA dest_unused operand");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2742 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )
2756 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
2777 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,
2789 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, AMDGPUAsmVariants::DPP
2905 SIInstrFlags::SDWA)) {
3156 if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc))
3367 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0)
3393 return (Desc.TSFlags & SIInstrFlags::SDWA) == 0 && !IsRevOpcode(Opcode);
6948 using namespace llvm::AMDGPU::SDWA;
6981 using namespace llvm::AMDGPU::SDWA;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp294 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
1127 using namespace AMDGPU::SDWA;
1175 using namespace AMDGPU::SDWA;

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