Searched refs:Rs (Results 1 - 25 of 31) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp109 // P0 = cmp.eq(Rs,#u2)
121 // Rd = Rs
162 // Rd=Rs ; jump #r9:2
200 MCOperand Rs, Rt; local
222 Rs = L.getOperand(1);
228 CompoundInsn->addOperand(Rs);
235 Rs = L.getOperand(1);
241 CompoundInsn->addOperand(Rs);
248 Rs = L.getOperand(1);
254 CompoundInsn->addOperand(Rs);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp636 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
639 Rs)));
641 Rs)));
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
653 Rs)));
655 Rs)));
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
680 if (Rs >= Rt) {
683 } else if (Rs != 0 && Rs < R
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
987 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1036 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1092 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1134 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1152 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
2561 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
2610 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
43 return (Opcode | Rs << 21 | Rt << 16 | Imm);
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
H A Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
44 return (Opcode | Rs << 21 | Rt << 16 | Imm);
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp279 // In memw(Rs+##V), the ##V could be replaced by a register Rt to
280 // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
282 // another instruction memw(Rs+##V+4), it would need a different Rt.
283 // Now, if Rt was initialized as "##V+Rs<<0", both of these
290 // Include shifting the Rs to account for the ur addressing mode:
291 // ##Val + Rs << S
292 // ##Val - Rs
293 Register Rs; member in struct:__anon4108::HexagonConstExtenders::ExtExpr
298 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
301 return Rs
447 HCE::Register Rs; member in struct:__anon4108::PrintRegister
1505 Register Rs = ExtI.second.Rs; // Only one reg allowed now. local
1802 Register Rs = MI.getOperand(IsSub ? 3 : 2); local
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H A DHexagonSplitDouble.cpp103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second; local
148 if (Rs.find(Reg) != Rs.end())
375 Register Rs = MI->getOperand(1).getReg(); local
377 return profit(Rs) + profit(Rt);
477 USet &Rs) {
561 Rs.insert(DP.begin(), End);
562 Rs.insert(CmpR1);
563 Rs
476 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) argument
584 USet Rs; local
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H A DHexagonGenInsert.cpp129 RegisterSet &insert(const RegisterSet &Rs) { argument
130 return static_cast<RegisterSet&>(BitVector::operator|=(Rs));
132 RegisterSet &remove(const RegisterSet &Rs) { argument
133 return static_cast<RegisterSet&>(BitVector::reset(Rs));
156 bool includes(const RegisterSet &Rs) const {
158 return !Rs.BitVector::test(*this);
160 bool intersects(const RegisterSet &Rs) const {
161 return BitVector::anyCommon(Rs);
1233 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
1270 void IFOrdering::stats(const RegisterSet &Rs, unsigne
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H A DHexagonAsmPrinter.cpp409 MCOperand &Rs = Inst.getOperand(1); local
410 assert(Rs.isReg() && "Expected register and none was found");
411 unsigned Reg = RI->getEncodingValue(Rs.getReg());
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
486 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
537 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
H A DHexagonBitSimplify.cpp109 RegisterSet &insert(const RegisterSet &Rs) { argument
110 return static_cast<RegisterSet&>(BitVector::operator|=(Rs));
112 RegisterSet &remove(const RegisterSet &Rs) { argument
113 return static_cast<RegisterSet&>(BitVector::reset(Rs));
136 bool includes(const RegisterSet &Rs) const {
138 return !Rs.BitVector::test(*this);
140 bool intersects(const RegisterSet &Rs) const {
141 return BitVector::anyCommon(Rs);
1764 BitTracker::RegisterRef &Rs, BitTracker::RegisterRef &Rt);
1888 // set the inputs Rs an
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H A DHexagonBitTracker.cpp296 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
298 uint16_t I = Odd, Ws = Rs.width();
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
303 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
465 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
650 // Result: S2_asr_i_r_rnd Rs, u5-1
702 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
H A DHexagonFrameLowering.cpp143 // Rd = PS_alloca Rs, A
146 // Rs - minimum size (the actual allocated can be larger to accommodate
2540 // Rd = alloca Rs, #A
2542 // If Rs and Rd are different registers, use this sequence:
2543 // Rd = sub(r29, Rs)
2544 // r29 = sub(r29, Rs)
2549 // Rd = sub(r29, Rs)
2556 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
2558 // Rd = sub(r29, Rs)
2561 .addReg(Rs);
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H A DHexagonISelLowering.cpp2698 SDValue Rs[8];
2704 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2706 for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2708 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2711 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DScalarEvolutionDivision.cpp149 SmallVector<const SCEV *, 2> Qs, Rs; local
161 Rs.push_back(R);
166 Remainder = Rs[0];
171 Remainder = SE.getAddExpr(Rs);
/freebsd-13-stable/contrib/mandoc/
H A Dmdoc.h152 struct mdoc_rs Rs; member in union:mdoc_data
H A Dmdoc_markdown.c194 { md_cond_body, md_pre_Rs, NULL, NULL, NULL }, /* Rs */
1567 if (n->parent->tok == MDOC_Rs && n->parent->norm->Rs.quote_T)
1579 if (n->parent->tok == MDOC_Rs && n->parent->norm->Rs.quote_T)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { argument
155 switch (Rs) {
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); local
184 return DecodeSrcAddrMode(Rs, As);
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); local
190 return DecodeSrcAddrMode(Rs, As);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp138 Register Rs = TailAdd.getOperand(1).getReg(); local
140 Register Reg = Rs == GAReg ? Rt : Rs;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1407 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1630 MCOperand &Rs = Inst.getOperand(2); local
1640 TmpInst.addOperand(Rs);
1650 MCOperand &Rs = Inst.getOperand(2); local
1660 TmpInst.addOperand(Rs);
1670 MCOperand &Rs = Inst.getOperand(2); local
1680 TmpInst.addOperand(Rs);
1693 MCOperand &Rs = Inst.getOperand(1); local
1710 TmpInst.addOperand(Rs);
1723 if (Value == 0) { // convert to $Rd = $Rs
1726 MCOperand &Rs = Inst.getOperand(1); local
1736 MCOperand &Rs = Inst.getOperand(1); local
1778 MCOperand &Rs = Inst.getOperand(1); local
1795 MCOperand &Rs = Inst.getOperand(1); local
1924 MCOperand &Rs = Inst.getOperand(1); local
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/freebsd-13-stable/contrib/llvm-project/clang/lib/Tooling/Core/
H A DReplacement.cpp221 Replacements Rs(R);
230 Rs.getReplacementInChangedCode(Replace));
234 auto MergeShiftedReplaces = Rs.merge(ReplacesShiftedByRs);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1296 unsigned Rs = fieldFromInstruction(insn, 16, 5); local
1308 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1332 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1344 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1353 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
/freebsd-13-stable/contrib/openpam/misc/
H A Dgendoc.pl539 $mdoc .= ".Rs
651 .Rs
/freebsd-13-stable/contrib/ntp/sntp/ag-tpl/0-old/
H A DMdoc.pm100 The C<CODE> is called after a Rs/Re block is done. With a hash reference as a
200 def_macro('.Rs', sub { () } );
/freebsd-13-stable/contrib/ntp/sntp/ag-tpl/
H A DMdoc.pm127 The C<CODE> is called after a Rs/Re block is done. With a hash reference as a
227 def_macro('.Rs', sub { () } );
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4108 unsigned Rs = Inst.getOperand(0).getReg(); local
4111 if (RI->isSubRegisterEq(Rt, Rs) ||
4112 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
4121 unsigned Rs = Inst.getOperand(0).getReg(); local
4125 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
4126 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp1493 // shifted. The second is Rs, the amount to shift by, and the third specifies
1499 // {11-8} = Rs
1512 unsigned Rs = MO1.getReg();
1513 if (Rs) {
1530 // Encode the shift operation Rs.
1531 // Encode Rs bit[11:8].
1533 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);

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