| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 453 LLT RegTy = MRI.getType(Op.getReg()); local
455 if (RegTy.isScalar() &&
456 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64))
459 if (RegTy.isVector() && RegTy.getSizeInBits() != 128)
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| H A D | MipsISelLowering.cpp | 4365 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4366 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4374 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4394 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); local
4406 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4433 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4445 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4449 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4484 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); local
4485 const TargetRegisterClass *RC = getRegClassFor(RegTy);
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); local
177 if (RegTy.isVector()) {
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements())
183 RegTy.getSizeInBits()) &&
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() ==
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| H A D | LegalizerHelper.cpp | 150 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, argument
156 unsigned RegSize = RegTy.getSizeInBits();
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 92 const LLT RegTy = MRI.getType(ValVReg); variable
93 MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
199 const LLT RegTy = MRI.getType(ValVReg); variable
200 if (RegTy.getSizeInBytes() > Size)
201 Size = RegTy.getSizeInBytes();
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 95 const LLT RegTy = getType(Reg); local
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
98 RegTy != ConstrainingRegTy)
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 1533 const LLT RegTy = MRI.getType(DstReg); local
1534 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1609 [RegTy](const DivRemEntry &El) {
1610 return El.SizeInBits == RegTy.getSizeInBits();
1636 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
1662 if (RegTy.getSizeInBits() == 16) {
1666 } else if (RegTy.getSizeInBits() == 32) {
1670 } else if (RegTy.getSizeInBits() == 64) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.h | 176 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
182 /// RegTy from smaller parts. This will produce a G_MERGE_VALUES,
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 137 const LLT RegTy = MRI.getType(ValVReg); variable
138 MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
|
| H A D | AMDGPULegalizerInfo.cpp | 3917 LLT RegTy;
3922 RegTy = S32;
3929 RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
3983 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy);
4013 if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 206 struct RegTy { struct in struct:__anon4092::HexagonOperand
220 struct RegTy Reg;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1503 template <VecListIndexType RegTy, unsigned NumRegs>
1518 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) &&
1521 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
1523 FirstRegs[(unsigned)RegTy][0]));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3041 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; local
3046 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);
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| /freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | TargetInfo.cpp | 5283 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
5284 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
|