Searched refs:RegNum (Results 1 - 25 of 40) sorted by relevance

12

/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
74 DwarfLLVMRegPair Key = { RegNum, 0 };
76 if (I == M+Size || I->FromReg != RegNum)
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
88 DwarfLLVMRegPair Key = { RegNum, 0 };
90 if (I != M + Size && I->FromReg == RegNum)
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true))
106 return RegNum;
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) cons
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp33 enum RegNum : uint32_t {
104 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
106 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
108 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr);
110 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
112 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
114 PatchOpcodes::PO_JALR, RegNum
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H A Dxray_mips64.cpp34 enum RegNum : uint32_t {
104 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8);
106 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0);
108 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr);
110 encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9,
113 PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
46 // allocated yet. RegNum is actually an index into ArgRegs, which means we
47 // need to skip a register if RegNum is odd.
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
49 State.AllocateReg(ArgRegs[RegNum]);
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
68 int RegsLeft = NumArgRegs - RegNum;
72 if (RegNum != NumArgRegs && RegsLeft < 4) {
74 State.AllocateReg(ArgRegs[RegNum
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.h47 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo);
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
98 return getRegisterName(RegNum);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp207 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, argument
209 return std::make_unique<AVROperand>(RegNum, S, E);
218 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { argument
219 return std::make_unique<AVROperand>(RegNum, Val, S, E);
339 int RegNum = matchFn(Name); local
345 if (RegNum == AVR::NoRegister) {
346 RegNum = matchFn(Name.lower());
348 if (RegNum == AVR::NoRegister) {
349 RegNum = matchFn(Name.upper());
352 return RegNum;
356 int RegNum = parseRegisterName(&MatchRegisterName); local
365 int RegNum = AVR::NoRegister; local
723 int64_t RegNum = Const->getValue(); local
725 RegName << "r" << RegNum; local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp207 unsigned RegNum; member in struct:__anon4092::HexagonOperand::RegTy
254 return Reg.RegNum;
433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { argument
435 Op->Reg.RegNum = RegNum;
1779 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
1780 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1782 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1787 std::string Name = r + utostr(RegNum
1796 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
1813 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
1833 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
1856 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp199 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, argument
201 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E);
209 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, argument
212 return std::make_unique<MSP430Operand>(RegNum, Val, S, E);
215 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, argument
217 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E);
220 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, argument
222 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp315 unsigned RegNum; member in struct:__anon3880::AArch64Operand::RegOp
341 unsigned RegNum; member in struct:__anon3880::AArch64Operand::VectorListOp
545 return Reg.RegNum;
555 return VectorList.RegNum;
1044 Reg.RegNum) ||
1046 Reg.RegNum));
1121 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
1126 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
1132 Reg.RegNum);
1138 Reg.RegNum);
1827 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) argument
1846 CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth, SMLoc S, SMLoc E, MCContext &Ctx, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) argument
1861 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E, MCContext &Ctx) argument
2274 unsigned RegNum = 0; local
2316 tryParseScalarRegister(unsigned &RegNum) argument
3168 unsigned RegNum = matchRegisterNameAlias(Head, MatchKind); local
3193 unsigned RegNum; local
3465 unsigned RegNum; local
3500 unsigned RegNum; local
5427 unsigned RegNum; local
5737 unsigned RegNum; local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
123 unsigned RegNum; member in struct:__anon4170::LanaiOperand::RegOp
158 return Reg.RegNum;
594 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, argument
597 Op->Reg.RegNum = RegNum;
698 unsigned RegNum; local
705 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier());
706 if (RegNum == 0) {
712 return LanaiOperand::createReg(RegNum, Star
719 ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) argument
730 tryParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackMaps.cpp93 int RegNum = TRI->getDwarfRegNum(Reg, false); local
94 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
95 RegNum = TRI->getDwarfRegNum(*SR, false);
97 assert(RegNum >= 0 && "Invalid Dwarf register number.");
98 return (unsigned)RegNum;
473 /// uint16 : Dwarf RegNum
479 /// uint16 : Dwarf RegNum
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h506 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
510 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
514 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
518 int getSEHRegNum(MCRegister RegNum) const;
522 int getCodeViewRegNum(MCRegister RegNum) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp170 unsigned RegNum; member in struct:__anon4344::VEOperand::RegOp
332 return Reg.RegNum;
578 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, argument
581 Op->Reg.RegNum = RegNum;
629 Op.Reg.RegNum = I32Regs[regIdx];
638 Op.Reg.RegNum = F32Regs[regIdx];
647 Op.Reg.RegNum = F128Regs[regIdx / 2];
659 Op.Reg.RegNum = MISCRegs[regIdx];
781 int RegNum local
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h847 int64_t RegNum = MatchTable[CurrentIdx++]; local
849 OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
852 << InsnID << "], " << RegNum << ")\n"); local
858 int64_t RegNum = MatchTable[CurrentIdx++]; local
860 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
863 << InsnID << "], " << RegNum << ")\n"); local
869 int64_t RegNum = MatchTable[CurrentIdx++]; local
872 OutMIs[InsnID].addReg(RegNum, RegFlags);
876 << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp90 unsigned RegNum; member in struct:__anon4071::BPFOperand::RegOp
150 return Reg.RegNum;
209 Op->Reg.RegNum = RegNo;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp280 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
282 if (30 == RegNum) {
287 return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.h26 const char *getVerboseConditionRegName(unsigned RegNum,
H A DPPCInstPrinter.cpp545 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, argument
550 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp233 unsigned RegNum; member in struct:__anon4304::SparcOperand::RegOp
289 return Reg.RegNum;
389 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument
392 Op->Reg.RegNum = RegNum;
422 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
433 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
456 Op.Reg.RegNum = Reg;
469 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
/freebsd-13-stable/contrib/llvm-project/clang/lib/Basic/
H A DTargetInfo.cpp510 if (AN == Name && ARN.RegNum < Names.size())
551 if (AN == Name && ARN.RegNum < Names.size())
552 return ReturnCanonical ? Names[ARN.RegNum] : Name;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp346 unsigned RegNum = TRI->getEncodingValue(Reg); local
351 FPUBitmask |= (1 << RegNum);
354 FPUBitmask |= (3 << RegNum);
358 CPUBitmask |= (1 << RegNum);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1070 unsigned &RegNum, unsigned &RegWidth,
1073 unsigned &RegNum, unsigned &RegWidth,
1075 unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1078 unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1081 unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1085 unsigned RegNum,
2174 unsigned RegNum,
2186 if (RegNum % AlignSize != 0)
2189 unsigned RegIdx = RegNum / AlignSize;
2230 unsigned &RegNum, unsigne
2173 getRegularReg(RegisterKind RegKind, unsigned RegNum, unsigned RegWidth) argument
2229 ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2244 ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2272 ParseRegList(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2311 ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2328 ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, unsigned &RegNum, unsigned &RegWidth, bool RestoreOnFailure) argument
2399 unsigned Reg, RegNum, RegWidth; local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp826 unsigned RegNum; member in struct:__anon4036::ARMOperand::RegOp
831 unsigned RegNum; member in struct:__anon4036::ARMOperand::VectorListOp
860 unsigned RegNum; member in struct:__anon4036::ARMOperand::PostIdxRegOp
966 return Reg.RegNum;
1443 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1964 VectorList.RegNum);
1970 .contains(VectorList.RegNum));
1987 .contains(VectorList.RegNum));
2003 VectorList.RegNum);
2022 .contains(VectorList.RegNum));
2411 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local
2418 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; local
2425 unsigned RegNum; local
3499 CreateCCOut(unsigned RegNum, SMLoc S) argument
3516 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument
3633 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3647 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3659 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3709 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3970 unsigned RegNum = MatchRegisterName(lowerCase); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp144 uint64_t RegNum = Data.getULEB128(C); local
145 addInstruction(Opcode, RegNum, 0);

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