/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( local 22 unsigned SlotSize = RegInfo->getSlotSize();
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H A D | X86CallFrameOptimization.cpp | 114 const X86RegisterInfo &RegInfo, 242 const X86RegisterInfo &RegInfo = local 244 SlotSize = RegInfo.getSlotSize(); 281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { 341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) 345 if (RegInfo.regsOverlap(Reg, U)) 359 const X86RegisterInfo &RegInfo = local 383 Register StackPtr = RegInfo.getStackRegister(); 415 Classification = classifyInstruction(MBB, I, RegInfo, UsedReg 279 classifyInstruction( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.h | 26 const NVPTXRegisterInfo RegInfo; member in class:llvm::NVPTXInstrInfo 31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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H A D | NVPTXInstrInfo.cpp | 30 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {} 40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
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/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
H A D | RegisterContextPOSIX_arm.h | 48 struct RegInfo { struct in class:RegisterContextPOSIX_arm 79 RegInfo m_reg_info;
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H A D | RegisterContextPOSIX_s390x.h | 47 struct RegInfo { struct in class:RegisterContextPOSIX_s390x 57 RegInfo m_reg_info;
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H A D | RegisterContextPOSIX_x86.h | 112 struct RegInfo { struct in class:RegisterContextPOSIX_x86 139 RegInfo m_reg_info;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in class:__anon4228::ExpandPseudo 102 RegInfo(*Subtarget.getRegisterInfo()) {} 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); 211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); 215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 408 const MipsRegisterInfo &RegInfo = local 696 const MipsRegisterInfo &RegInfo = local [all...] |
H A D | Mips16ISelDAGToDAG.cpp | 72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 78 V0 = RegInfo.createVirtualRegister(RC); 79 V1 = RegInfo.createVirtualRegister(RC); 80 V2 = RegInfo.createVirtualRegister(RC);
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H A D | MipsSERegisterInfo.cpp | 156 const MipsRegisterInfo *RegInfo = local 183 else if (RegInfo->needsStackRealignment(MF)) { 224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); local 225 Register Reg = RegInfo.createVirtualRegister(PtrRC);
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H A D | MipsMachineFunction.cpp | 68 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local 76 Register V0 = RegInfo.createVirtualRegister(RC); 77 Register V1 = RegInfo.createVirtualRegister(RC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = local 100 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); 156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); 169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); 170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); 251 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 255 RegInfo->needsStackRealignment(MF) || 265 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local 283 } else if (RegInfo->needsStackRealignment(MF)) { 297 FrameReg = RegInfo [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 119 const ThumbRegisterInfo *RegInfo = local 137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 140 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 154 const ThumbRegisterInfo *RegInfo = local 169 Register FramePtr = RegInfo->getFrameRegister(MF); 170 unsigned BasePtr = RegInfo->getBaseRegister(); 183 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 195 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, 386 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 406 if (RegInfo 478 const ThumbRegisterInfo *RegInfo = local 608 const ThumbRegisterInfo *RegInfo = local 818 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( local 939 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( local [all...] |
H A D | ARMFrameLowering.cpp | 105 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 113 return (RegInfo->needsStackRealignment(MF) || 345 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); local 360 Register FramePtr = RegInfo->getFrameRegister(MF); 714 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 746 if (RegInfo->hasBasePointer(MF)) { 748 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 753 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) 769 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 778 Register FramePtr = RegInfo 895 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( local 1672 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( local [all...] |
H A D | Thumb1InstrInfo.cpp | 58 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); local 59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) 63 ->addRegisterDead(ARM::CPSR, RegInfo);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
H A D | DWARFExpression.h | 97 const MCRegisterInfo *RegInfo, DWARFUnit *U, bool isEH); 146 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo, DWARFUnit *U, 153 bool printCompact(raw_ostream &OS, const MCRegisterInfo &RegInfo);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetRegisterInfo.cpp | 173 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, 175 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { 176 if (RegInfo.getRegClassOrNull(Reg)) 177 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); 178 else if (RegInfo.getRegBankOrNull(Reg)) 179 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); 182 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
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H A D | DetectDeadLanes.cpp | 105 const VRegInfo &RegInfo) const; 300 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; local 301 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; 306 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; 459 const VRegInfo &RegInfo) const { 462 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); 543 const VRegInfo &RegInfo = VRegInfos[RegIdx]; local 544 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { 551 if (isUndefRegAtInput(MO, RegInfo)) { [all...] |
H A D | MIRPrinter.cpp | 125 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, 268 const MachineRegisterInfo &RegInfo, 271 OS << printRegClassOrBank(Reg, RegInfo, TRI); 291 const MachineRegisterInfo &RegInfo, 293 MF.TracksRegLiveness = RegInfo.tracksLiveness(); 296 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { 300 if (RegInfo.getVRegName(Reg) != "") 302 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); 303 unsigned PreferredReg = RegInfo.getSimpleHint(Reg); 310 for (std::pair<unsigned, unsigned> LI : RegInfo 267 printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) argument 290 convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 125 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 126 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVSubtarget.h | 65 RISCVRegisterInfo RegInfo; member in class:llvm::RISCVSubtarget 89 return &RegInfo;
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H A D | RISCVSubtarget.cpp | 55 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZLDCleanup.cpp | 134 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local 135 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEFrameLowering.cpp | 211 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); local 216 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); 261 Register RegFP = RegInfo.getDwarfRegNum(VE::SX9, true); 308 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local 312 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || 326 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); local 338 if (RegInfo->needsStackRealignment(MF) && !isFixed) { 349 FrameReg = RegInfo->getFrameRegister(MF);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
H A D | ControlHeightReduction.cpp | 162 // RegInfo - some properties of a Region. 163 struct RegInfo { struct in namespace:__anon4576 164 RegInfo() : R(nullptr), HasBranch(false) {} function in struct:__anon4576::RegInfo 165 RegInfo(Region *RegionIn) : R(RegionIn), HasBranch(false) {} function in struct:__anon4576::RegInfo 178 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { 231 for (RegInfo &RI : RegInfos) 248 RegInfos, [&Boundary](const RegInfo &RI) { return Boundary == RI.R; }); 251 ArrayRef<RegInfo> TailRegInfos(BoundaryIt, RegInfos.end()); 253 for (const RegInfo &RI : TailRegInfos) 264 [&Parent](const RegInfo [all...] |