Searched refs:RegA (Results 1 - 7 of 7) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86WinAllocaExpander.cpp | 220 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; local
222 .addReg(RegA, RegState::Undef);
234 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; local
236 .addReg(RegA, RegState::Undef);
248 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; local
249 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 552 /// Returns true if RegB is a sub-register of RegA.
553 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
554 return isSuperRegister(RegB, RegA);
557 /// Returns true if RegB is a super-register of RegA.
558 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
560 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
561 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
562 return isSuperRegisterEq(RegB, RegA);
565 /// Returns true if RegB is a super-register of RegA o
649 isSuperRegister(MCRegister RegA, MCRegister RegB) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 131 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
135 unsigned RegA, unsigned RegB, unsigned Dist);
423 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { argument
424 if (RegA == RegB)
426 if (!RegA || !RegB)
428 return TRI->regsOverlap(RegA, RegB);
489 // -RegB is not tied to a register and RegC is compatible with RegA.
495 // -RegC is not tied to a register and RegB is compatible with RegA.
564 Register RegA = MI->getOperand(DstIdx).getReg(); local
565 SrcRegMap[RegA]
574 isProfitableToConv3Addr(unsigned RegA,unsigned RegB) argument
591 convertInstTo3Addr(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned RegA, unsigned RegB, unsigned Dist) argument
1370 Register RegA = DstMO.getReg(); local
[all...] |
| H A D | ImplicitNullChecks.cpp | 282 Register RegA = MOA.getReg(); local
289 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
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| H A D | TargetInstrInfo.cpp | 817 Register RegA = OpA.getReg(); local
823 if (Register::isVirtualRegister(RegA))
824 MRI.constrainRegClass(RegA, RC);
852 .addReg(RegA, getKillRegState(KillA))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2129 for (auto &RegA : DefsA)
2132 if (RegA == RegB)
2135 if (Register::isPhysicalRegister(RegA))
2136 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2142 if (RegA == *SubRegs)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 407 Register RegA = Prev->getOperand(AddOpIdx).getReg(); local
408 MachineInstr *Leaf = MRI.getUniqueVRegDef(RegA);
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