| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 48 bool SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt);
49 bool SelectSROI(SDValue N, SDValue &RS1, SDValue &Shamt);
50 bool SelectRORI(SDValue N, SDValue &RS1, SDValue &Shamt);
51 bool SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt);
52 bool SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt);
53 bool SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt);
54 bool SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt);
55 bool SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, SDValue &Shamt);
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| H A D | RISCVISelDAGToDAG.cpp | 190 // (OR (SHL RS1, VC2), VC1)
197 bool RISCVDAGToDAGISel::SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt) { argument
209 RS1 = Shl.getOperand(0);
219 RS1 = Shl.getOperand(0);
234 // (OR (SRL RS1, VC2), VC1)
241 bool RISCVDAGToDAGISel::SelectSROI(SDValue N, SDValue &RS1, SDValue &Shamt) { argument
253 RS1 = Srl.getOperand(0);
263 RS1 = Srl.getOperand(0);
278 // (ROTL RS1, VC)
289 bool RISCVDAGToDAGISel::SelectRORI(SDValue N, SDValue &RS1, SDValu argument
328 SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt) argument
359 SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt) argument
394 SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt) argument
429 SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) argument
476 SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, SDValue &Shamt) argument
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 124 static void emitLEAzii(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, argument
131 LEAInst.addOperand(RS1);
136 static void emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1, argument
142 LEASLInst.addOperand(RS1);
148 static void emitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, argument
154 Inst.addOperand(RS1);
159 static void emitANDrm(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, argument
161 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
132 Inst.addOperand(RS1);
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
150 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
152 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
125 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
137 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
143 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument
149 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 923 unsigned RS1 = getRegState(Op1); local
947 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
950 .addReg(Op1.getReg(), RS1, HiSR)
954 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
964 .addReg(Op1.getReg(), RS1, HiSR)
976 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
978 .addReg(Op1.getReg(), RS1, HiSR)
987 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
989 .addReg(Op1.getReg(), RS1, HiSR)
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