Lines Matching refs:RS1
190 // (OR (SHL RS1, VC2), VC1)
197 bool RISCVDAGToDAGISel::SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt) {
209 RS1 = Shl.getOperand(0);
219 RS1 = Shl.getOperand(0);
234 // (OR (SRL RS1, VC2), VC1)
241 bool RISCVDAGToDAGISel::SelectSROI(SDValue N, SDValue &RS1, SDValue &Shamt) {
253 RS1 = Srl.getOperand(0);
263 RS1 = Srl.getOperand(0);
278 // (ROTL RS1, VC)
289 bool RISCVDAGToDAGISel::SelectRORI(SDValue N, SDValue &RS1, SDValue &Shamt) {
297 RS1 = N.getOperand(0);
304 RS1 = N.getOperand(0);
316 // XLEN-1:32 of the input RS1 before shifting.
319 // (AND (SHL RS1, VC2), VC1)
324 // of RS1, is correct:
328 bool RISCVDAGToDAGISel::SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt) {
338 RS1 = Shl.getOperand(0);
352 // (SIGN_EXTEND_INREG (OR (SHL RS1, VC2), VC1))
359 bool RISCVDAGToDAGISel::SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
372 RS1 = Shl.getOperand(0);
387 // (OR (SHL RS1, VC2), VC1)
394 bool RISCVDAGToDAGISel::SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
404 RS1 = Srl.getOperand(0);
418 // (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
429 bool RISCVDAGToDAGISel::SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
449 RS1 = Shl.getOperand(0);
465 // (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
476 bool RISCVDAGToDAGISel::SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2,
497 RS1 = Shl.getOperand(0);