Searched refs:RCID (Results 1 - 13 of 13) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h147 bool isSGPRClassID(unsigned RCID) const {
148 return isSGPRClass(getRegClass(RCID));
280 const TargetRegisterClass *getRegClass(unsigned RCID) const;
H A DAMDGPUTargetTransformInfo.h162 unsigned getNumberOfRegisters(unsigned RCID) const;
H A DAMDGPUTargetTransformInfo.cpp255 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const {
257 const TargetRegisterClass *RC = TRI->getRegClass(RCID);
H A DSIRegisterInfo.cpp1861 SIRegisterInfo::getRegClass(unsigned RCID) const {
1862 switch ((int)RCID) {
1871 return AMDGPUGenRegisterInfo::getRegClass(RCID);
H A DSIInstrInfo.cpp4158 unsigned RCID = Desc.OpInfo[OpNo].RegClass; local
4159 return RI.getRegClass(RCID);
4169 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; local
4170 const TargetRegisterClass *RC = RI.getRegClass(RCID);
6788 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; local
6789 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
H A DAMDGPUISelDAGToDAG.cpp588 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); local
590 Subtarget->getRegisterInfo()->getRegClass(RCID);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1371 unsigned RCID = 0; local
1373 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1375 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1377 OS << ":RC" << RCID; local
H A DMachineInstr.cpp892 unsigned RCID; local
896 InlineAsm::hasRegClassConstraint(Flag, RCID))
897 return TRI->getRegClass(RCID);
1696 unsigned RCID = 0;
1698 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1700 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1702 OS << ":RC" << RCID;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1121 unsigned getRegBitWidth(unsigned RCID) {
1122 switch (RCID) {
1193 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1194 return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
H A DAMDGPUBaseInfo.h590 unsigned getRegBitWidth(unsigned RCID);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp247 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { argument
248 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type);
368 bool isRegClass(unsigned RCID) const;
372 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { argument
373 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers();
1669 bool AMDGPUOperand::isRegClass(unsigned RCID) const {
1670 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
2190 int RCID = getRegClass(RegKind, RegWidth); local
2191 if (RCID == -1)
2195 const MCRegisterClass RC = TRI->getRegClass(RCID);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp632 int RCID = Desc.OpInfo[OpNo].RegClass; local
633 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1532 unsigned RCID; local
1550 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {

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