Searched refs:PrevReg (Results 1 - 8 of 8) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
822 unsigned PrevReg, unsigned CurReg) {
824 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal);
845 PrevMaskedReg = PrevReg;
849 .addReg(PrevReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DModuloSchedule.cpp563 unsigned PrevReg = 0; local
565 PrevReg = VRMap[PrevStage - np][LoopVal];
567 NewReg, PrevReg);
1145 unsigned PrevReg) {
1173 if (PrevReg && InProlog)
1174 ReplaceReg = PrevReg;
1175 else if (PrevReg && !isLoopCarried(*Phi) &&
1177 ReplaceReg = PrevReg;
1142 rewriteScheduledInstr( MachineBasicBlock *BB, InstrMapTy &InstrMap, unsigned CurStageNum, unsigned PhiNum, MachineInstr *Phi, unsigned OldReg, unsigned NewReg, unsigned PrevReg) argument
H A DRegAllocGreedy.cpp459 Register canReassign(LiveInterval &VirtReg, Register PrevReg);
802 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) { argument
806 if (PhysReg == PrevReg)
822 << printReg(PrevReg, TRI) << " to "
H A DMachinePipeliner.cpp2199 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); local
2200 if (!PrevReg)
2204 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg);
2229 NewBase = PrevReg;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h229 unsigned NewReg, unsigned PrevReg = 0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp539 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); local
552 PrevReg = MCRegOp;
575 TmpInst.addOperand(PrevReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3376 int64_t PrevReg = FirstReg;
3394 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
3420 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
3425 PrevReg = Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1422 int PrevReg = *RegList.List->begin(); local
1425 if ( Reg != PrevReg + 1)
1427 PrevReg = Reg;
6793 unsigned PrevReg = Mips::NoRegister; local
6812 unsigned TmpReg = PrevReg + 1;
6821 PrevReg = TmpReg;
6828 if ((PrevReg == Mips::NoRegister) &&
6841 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
6865 PrevReg
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