| /freebsd-13-stable/sys/arm64/qoriq/clk/ |
| H A D | lx2160a_clkgen.c | 51 #define PLL(_id1, _id2, cname, o, d) \ macro
69 PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
71 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);
73 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);
75 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);
77 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);
89 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cg_divs)},
91 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cg_divs)},
93 {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cg_divs)},
95 {PLL(QORIQ_TYPE_INTERNA
[all...] |
| /freebsd-13-stable/sys/riscv/sifive/ |
| H A D | fu540_prci.c | 109 #define PLL(_id, _name, _base) \ macro
116 /* PLL Clocks */
118 PLL(PRCI_CLK_COREPLL, "coreclk", PRCI_COREPLL_CFG0),
119 PLL(PRCI_CLK_DDRPLL, "ddrclk", PRCI_DDRPLL_CFG0),
120 PLL(PRCI_CLK_GEMGXLPLL, "gemgxclk", PRCI_GEMGXLPLL_CFG0),
168 /* Calculate the PLL output */
|
| /freebsd-13-stable/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 119 #define PLL(_id, cname, pname) \ macro
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
313 PLL(TEGRA124_CLK_PLL_
[all...] |
| /freebsd-13-stable/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 147 #define PLL(_id, cname, pname) \ macro
167 /* Fractional divider (7.1) for PLL branch. */
182 /* P divider (2^n). for PLL branch. */
195 /* P divider (2^n). for PLL branch. */
224 /* Gate for PLL branch. */
275 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
287 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
299 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
311 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
322 PLL(TEGRA210_CLK_PLL_C
[all...] |
| /freebsd-13-stable/sys/arm64/rockchip/clk/ |
| H A D | rk3399_cru.c | 687 /* Standard PLL. */
688 #define PLL(_id, _name, _base) \ macro
789 PLL(PLL_APLLL, "lpll", 0x00),
790 PLL(PLL_APLLB, "bpll", 0x20),
791 PLL(PLL_DPLL, "dpll", 0x40),
792 PLL(PLL_CPLL, "cpll", 0x60),
793 PLL(PLL_GPLL, "gpll", 0x80),
794 PLL(PLL_NPLL, "npll", 0xA0),
795 PLL(PLL_VPLL, "vpll", 0xC0),
|
| H A D | rk3288_cru.c | 524 /* Standard PLL. */
525 #define PLL(_id, _name, _base, _shift) \ macro
686 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
687 PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4),
688 PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8),
689 PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12),
690 PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14),
|
| /freebsd-13-stable/sys/mips/ingenic/ |
| H A D | jz4780_clock.c | 82 #define PLL(_id, cname, pname, reg) { \ macro
138 /* PLL definitions */
140 PLL(JZ4780_CLK_APLL, "apll", "ext", JZ_CPAPCR),
141 PLL(JZ4780_CLK_MPLL, "mpll", "ext", JZ_CPMPCR),
142 PLL(JZ4780_CLK_EPLL, "epll", "ext", JZ_CPEPCR),
143 PLL(JZ4780_CLK_VPLL, "vpll", "ext", JZ_CPVPCR),
716 /* Enable OTG, should not be necessary since we use PLL clock */
|