Lines Matching refs:PLL
119 #define PLL(_id, cname, pname) \
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
324 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
334 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
347 PLL(0, "pllREFE_out", "osc_div_clk"),
360 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
370 PLL(0, "pllDP_out0", "pllDP_src"),
550 printf("PLL lock timeout\n");
648 /* Enable HW control and unreset SATA PLL. */
664 /* Enable HW control of PCIe PLL. */
730 /* Enable PLL. */
742 /* Disable PLL */
909 /* Set PLL. */
924 /* Enable PLL. */
931 /* Disable PLL */
995 /* If PLL is enabled, enable lock detect too. */