Searched refs:OpReg (Results 1 - 15 of 15) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1715 Register OpReg = getRegForValue(TI->getOperand(0)); local
1716 if (OpReg == 0) return false;
1719 .addReg(OpReg).addImm(1);
1750 Register OpReg = getRegForValue(BI->getCondition()); local
1751 if (OpReg == 0) return false;
1753 // In case OpReg is a K register, COPY to a GPR
1754 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
1755 unsigned KOpReg = OpReg;
1756 OpReg = createResultReg(&X86::GR32RegClass);
1758 TII.get(TargetOpcode::COPY), OpReg)
1773 unsigned CReg = 0, OpReg = 0; local
2368 Register OpReg = getRegForValue(Opnd); local
2469 Register OpReg = getRegForValue(I->getOperand(0)); local
[all...]
H A DX86SpeculativeLoadHardening.cpp1661 Register OpReg = Op->getReg(); local
1662 auto *OpRC = MRI->getRegClass(OpReg);
1700 .addReg(OpReg);
1731 .addReg(OpReg);
1744 .addReg(OpReg);
1753 .addReg(OpReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp298 Register OpReg = MI->getOperand(I).getReg(); local
300 if (!Register::isVirtualRegister(OpReg))
303 MachineInstr *Def = MRI->getVRegDef(OpReg);
H A DARMInstructionSelector.cpp1045 Register OpReg = I.getOperand(2).getReg(); local
1046 unsigned Size = MRI.getType(OpReg).getSizeInBits();
H A DARMFastISel.cpp1263 unsigned OpReg = getRegForValue(TI->getOperand(0)); local
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1267 .addReg(OpReg).addImm(1));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1764 Register OpReg = getRegForValue(In); local
1765 if (!OpReg)
1772 OpReg, OpRegIsKill);
1787 ISD::BITCAST, OpReg, OpRegIsKill);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp3941 Register OpReg = MI.getOperand(0).getReg(); local
3943 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3950 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3956 // OpSegStart is where this destination segment would start in OpReg if it
4010 Register OpReg = MI.getOperand(2).getReg(); local
4012 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4020 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
4023 DstRegs.push_back(OpReg);
4027 // OpSegStart is where this destination segment would start in OpReg if it
4042 Register SegReg = OpReg;
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp1893 Register OpReg = MO.getReg();
1894 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4541 unsigned OpReg = Inst.getOperand(2).getReg(); local
4557 // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4678 unsigned OpReg = Inst.getOperand(2).getReg(); local
4694 // $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg))
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
5369 unsigned OpReg = Inst.getOperand(2).getReg(); local
5373 if (SrcReg != Mips::ZERO && OpReg !
5450 unsigned OpReg = Inst.getOperand(2).getReg(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2048 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
2059 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg)
2065 .addReg(OpReg)
2085 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
2100 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg)
2106 .addReg(OpReg)
H A DAMDGPURegisterBankInfo.cpp3202 Register OpReg = MI.getOperand(I).getReg();
3204 if (!OpReg)
3207 unsigned Size = getSizeInBits(OpReg, MRI, *TRI);
3217 unsigned NewBank = getRegBankID(OpReg, MRI, *TRI, AMDGPU::SGPRRegBankID);
H A DSIInstrInfo.cpp4616 Register OpReg = Op.getReg(); local
4620 RI.getRegClassForReg(MRI, OpReg), OpSubReg);
4633 MachineInstr *Def = MRI.getVRegDef(OpReg);
4639 FoldImmediate(*Copy, *Def, OpReg, &MRI);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); local
252 return getVectorRegSize(OpReg) / ScalarSize;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5592 Register OpReg = MO.getReg();
5593 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg);
5596 auto *OpDef = MRI.getVRegDef(OpReg);
5597 const LLT &Ty = MRI.getType(OpReg);
5599 auto Copy = MIB.buildCopy(Ty, OpReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7356 unsigned OpReg = Inst.getOperand(i).getReg(); local
7357 if (OpReg == Reg)
7360 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7370 unsigned OpReg = Inst.getOperand(i).getReg(); local
7371 if (OpReg == Reg)

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