Searched refs:Op5 (Results 1 - 5 of 5) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
659 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
681 unsigned Op1, Op2, Op3, Op4, Op5; local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
694 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1952 const T4 &Op4, const T5 &Op5) {
1954 m_Argument<5>(Op5));
1951 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3, const T4 &Op4, const T5 &Op5) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6528 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); local
6533 (Op5.isReg() && Op5.getReg() == ARM::PC);
6536 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6538 Op5.isImm() && !Op5.isImm0_508s4());
6557 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6559 const ARMOperand *LastOp = &Op5;
6561 if (!Transform && Op5
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1379 SDValue Op3, SDValue Op4, SDValue Op5);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7830 SDValue Op3, SDValue Op4, SDValue Op5) {
7831 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };

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