/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFrameLowering.cpp | 248 Register OffsetReg = MRI.createVirtualRegister(PtrRC); local 249 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) 253 .addReg(OffsetReg); 300 Register OffsetReg = MRI.createVirtualRegister(PtrRC); local 301 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) 309 .addReg(OffsetReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 51 unsigned OffsetReg, 57 unsigned OffsetReg, 247 unsigned OffsetReg) const; 255 unsigned OffsetReg) const;
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H A D | R600InstrInfo.cpp | 1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); 1041 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { 1046 OffsetReg); 1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); 1055 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { 1061 OffsetReg); 1116 unsigned OffsetReg) const { 1117 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); 1123 unsigned OffsetReg, 1134 R600::AR_X, OffsetReg); [all...] |
H A D | SIFrameLowering.cpp | 161 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( local 164 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) 169 .addReg(OffsetReg, RegState::Kill) 208 MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister( local 211 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg) 216 .addReg(OffsetReg, RegState::Kill)
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H A D | AMDGPUCallLowering.cpp | 407 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); local 409 return B.buildPtrAdd(PtrType, KernArgSegmentVReg, OffsetReg).getReg(0);
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H A D | SIRegisterInfo.cpp | 467 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); local 471 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) 477 .addReg(OffsetReg, RegState::Kill)
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H A D | AMDGPUInstructionSelector.cpp | 3105 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 3106 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg) 3110 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
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H A D | AMDGPURegisterBankInfo.cpp | 1532 Register OffsetReg = MI.getOperand(3).getReg(); local 1544 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 132 unsigned OffsetReg; member in struct:__anon4170::LanaiOperand::MemOp 178 return Mem.OffsetReg; 618 Op->Mem.OffsetReg = 0; 626 unsigned OffsetReg = Op->getReg(); local 630 Op->Mem.OffsetReg = OffsetReg; 642 Op->Mem.OffsetReg = 0;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; local 571 OffsetReg = MI->getOperand(2).getReg(); 606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); 609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
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H A D | ARMCallLowering.cpp | 104 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); variable 106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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H A D | Thumb2InstrInfo.cpp | 566 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); 567 if (OffsetReg != 0) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 114 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); variable 116 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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H A D | X86ISelLowering.cpp | [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 243 unsigned OffsetReg; member in struct:__anon4304::SparcOperand::MemOp 304 return Mem.OffsetReg; 479 Op->Mem.OffsetReg = offsetReg; 488 Op->Mem.OffsetReg = Sparc::G0; // always 0 500 Op->Mem.OffsetReg = 0;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonOptAddrMode.cpp | 166 Register OffsetReg = MI.getOperand(2).getReg(); 171 if (OffsetReg == RR.Reg) {
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H A D | HexagonISelLowering.cpp | 3004 unsigned OffsetReg = Hexagon::R28; local 3010 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); 3013 // MF.getRegInfo().addLiveOut(OffsetReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 267 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); local 269 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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H A D | MipsSEInstrInfo.cpp | 887 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 895 Register OffsetReg = I->getOperand(0).getReg(); local 909 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
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H A D | MipsISelLowering.cpp | 2558 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; local 2560 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2563 DAG.getRegister(OffsetReg, Ty),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 162 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); variable 164 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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H A D | AArch64InstructionSelector.cpp | 4931 Register OffsetReg = OffsetInst->getOperand(1).getReg(); 4941 std::swap(OffsetReg, ConstantReg); 4974 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); 4983 OffsetReg = ExtInst->getOperand(1).getReg(); 4988 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); 4994 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); },
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 94 unsigned OffsetReg = 0; member in class:__anon3849::final::Address 120 OffsetReg = Reg; 124 return OffsetReg;
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