Searched refs:NewSrc (Results 1 - 8 of 8) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 1198 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap, local
1200 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0)
1204 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1205 // We may have extended the live-range of NewSrc, account for that.
1206 MRI->clearKillFlags(NewSrc.Reg);
1231 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); local
1240 .addReg(NewSrc.Reg, 0, NewSrc
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 251 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
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| H A D | X86InstrInfo.cpp | 1188 unsigned Opc, bool AllowSP, Register &NewSrc,
1204 NewSrc = SrcReg;
1208 if (Register::isVirtualRegister(NewSrc) &&
1209 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1221 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1227 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1230 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1187 classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned Opc, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV) const argument
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| H A D | X86ISelLowering.cpp | [all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1054 SDValue NewSrc = SimplifyMultipleUseDemandedBits( local
1056 if (NewSub || NewSrc) {
1058 NewSrc = NewSrc ? NewSrc : Src;
1059 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc, NewSub,
1936 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1938 return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc));
1953 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1955 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc));
2536 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( local
2568 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( local
[all...] |
| H A D | LegalizeVectorTypes.cpp | 1802 SDValue NewSrc = local
1805 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1984 // put NewSrc at same location as %src
1986 auto *NewSrc = cast<GetElementPtrInst>( local
1988 NewSrc->setIsInBounds(Src->isInBounds());
1989 auto *NewGEP = GetElementPtrInst::Create(GEPEltType, NewSrc, {SO1});
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.cpp | 4283 TreePatternNodePtr NewSrc = P.SrcPattern->clone();
4285 if (!NewSrc->setDefaultMode(Mode) || !NewDst->setDefaultMode(Mode)) {
4292 PatternsToMatch.emplace_back(P.getSrcRecord(), Preds, std::move(NewSrc),
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