Searched refs:LoHalf (Results 1 - 5 of 5) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 627 return OpRef(R.OpN & (Undef | Index | LoHalf));
647 LoHalf = 0x20000000,
649 Whole = LoHalf | HiHalf,
724 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf);
725 if (OpN & LoHalf)
1011 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf);
1014 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1669 MachineInstr *LoHalf = local
1675 (void)LoHalf;
1676 LLVM_DEBUG(dbgs() << " "; LoHalf->dump(););
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| H A D | SIInstrInfo.cpp | 5793 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); local
5810 Worklist.insert(&LoHalf);
5859 MachineInstr *LoHalf = local
5885 legalizeOperands(*LoHalf, MDT);
5931 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) local
5949 Worklist.insert(&LoHalf);
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| H A D | SIISelLowering.cpp | 3853 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) local
3873 TII->legalizeOperands(*LoHalf);
5260 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, local
5265 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
5279 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4836 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); local
4845 .addDef(LoHalf)
4853 .addUse(LoHalf);
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