Searched refs:LastStage (Results 1 - 7 of 7) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h101 uint16_t LastStage; ///< Index of last + 1 stage in itinerary member in struct:llvm::InstrItinerary
131 (Itineraries[ItinClassIndx].LastStage == UINT16_MAX));
142 unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.h72 LastStage = ClusteredLowOccupancyReschedule
H A DGCNSchedStrategy.cpp610 } while (Stage != LastStage);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h190 void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
192 void generateEpilog(unsigned LastStage, MachineBasicBlock *KernelBB,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DModuloSchedule.cpp192 void ModuloScheduleExpander::generateProlog(unsigned LastStage, argument
202 for (unsigned i = 0; i < LastStage; ++i) {
250 void ModuloScheduleExpander::generateEpilog(unsigned LastStage, argument
277 int EpilogStage = LastStage + 1;
278 for (unsigned i = LastStage; i >= 1; --i, ++EpilogStage) {
291 for (unsigned StageNum = i; StageNum <= LastStage; ++StageNum) {
307 InstrMap, LastStage, EpilogStage, i == 1);
309 LastStage, EpilogStage, i == 1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp429 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
435 unsigned Stage = II[SchedClass].LastStage - 1;
465 Stage < II[SchedClass].LastStage; ++Stage) {
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp594 Intinerary.LastStage << ", " <<

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