Searched refs:InitReg (Results 1 - 4 of 4) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1262 // Map from <LoopReg, InitReg> to phi register for all created phis. Note that
1263 // this map is only used when InitReg is non-undef.
1265 // Map from LoopReg to phi register where the InitReg is undef.
1271 // Insert a phi that carries LoopReg from the loop body and InitReg otherwise.
1272 // If InitReg is not given it is chosen arbitrarily. It will either be undef
1274 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1459 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, argument
1462 if (InitReg.hasValue()) {
1463 auto I = Phis.find({LoopReg, InitReg.getValue()});
1473 // InitReg i
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDILCFGStructurizer.cpp | 1320 Register InitReg = local
1322 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg,
|
| H A D | AMDGPURegisterBankInfo.cpp | 756 Register InitReg = B.buildUndef(ResTy).getReg(0); local
758 InitResultRegs.push_back(InitReg);
761 MRI.setRegBank(InitReg, *DefBank);
|
| H A D | SIISelLowering.cpp | 3367 unsigned InitReg,
3386 .addReg(InitReg)
3639 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
3641 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3643 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3360 emitLoadM0FromVGPRLoop( const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument
|
Completed in 233 milliseconds