Searched refs:ISD (Results 1 - 25 of 155) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp62 if (getOpcode() < ISD::BUILTIN_OP_END)
80 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
82 case ISD::PREFETCH: return "Prefetch";
83 case ISD::ATOMIC_FENCE: return "AtomicFence";
84 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
85 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
86 case ISD::ATOMIC_SWAP: return "AtomicSwap";
87 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
88 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
89 case ISD
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H A DLegalizeVectorOps.cpp14 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
15 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
21 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
257 if (Op.getOpcode() == ISD::LOAD) {
259 ISD::LoadExtType ExtType = LD->getExtensionType();
260 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
288 } else if (Op.getOpcode() == ISD::STORE) {
332 case ISD::MERGE_VALUES:
340 case ISD
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H A DLegalizeDAG.cpp319 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
334 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
408 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
426 if (!ISD::isNormalStore(ST))
478 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
503 switch (TLI.getOperationAction(ISD::STORE, VT)) {
527 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
530 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
583 ISD::SRL, dl, Value.getValueType(), Value,
594 ISD
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H A DLegalizeIntegerTypes.cpp55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
63 case ISD::CTLZ_ZERO_UNDEF:
64 case ISD
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H A DLegalizeVectorTypes.cpp51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD
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H A DTargetLowering.cpp94 if (Value->getOpcode() != ISD::CopyFromReg)
227 if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
231 isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
277 ISD::CondCode &CCCode,
287 ISD::CondCode &CCCode,
303 case ISD::SETEQ:
304 case ISD::SETOEQ:
309 case ISD::SETNE:
310 case ISD::SETUNE:
315 case ISD
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H A DDAGCombiner.cpp262 assert(N->getOpcode() != ISD::DELETED_NODE &&
267 if (N->getOpcode() == ISD::HANDLENODE)
366 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
369 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
537 SDValue N2, SDValue N3, ISD::CondCode CC,
541 ISD::CondCode CC);
543 SDValue N2, SDValue N3, ISD::CondCode CC);
548 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
646 if (StoreVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
647 StoreVal.getOpcode() == ISD
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H A DLegalizeFloatTypes.cpp61 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
62 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
63 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
64 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
68 case ISD::STRICT_FMINNUM:
69 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
70 case ISD::STRICT_FMAXNUM:
71 case ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp188 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
189 assert(ISD && "Invalid opcode");
192 { ISD::FDIV, MVT::f32, 18 }, // divss
193 { ISD::FDIV, MVT::v4f32, 35 }, // divps
194 { ISD::FDIV, MVT::f64, 33 }, // divsd
195 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
199 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
205 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
206 { ISD
1372 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
2067 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
2568 unsigned ISD = ISD::DELETED_NODE; local
2776 unsigned ISD = ISD::DELETED_NODE; local
2868 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
3161 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
3366 int ISD; local
3496 int ISD; local
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H A DX86CallingConv.h24 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCostTable.h25 int ISD; member in struct:llvm::CostTblEntry
32 int ISD, MVT Ty) {
34 return ISD == Entry.ISD && Ty == Entry.Type;
45 int ISD; member in struct:llvm::TypeConversionCostTblEntry
55 int ISD, MVT Dst, MVT Src) {
57 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
31 CostTableLookup(ArrayRef<CostTblEntry> Tbl, int ISD, MVT Ty) argument
54 ConvertCostTableLookup(ArrayRef<TypeConversionCostTblEntry> Tbl, int ISD, MVT Dst, MVT Src) argument
H A DSelectionDAGNodes.h84 namespace ISD { namespace in namespace:llvm
109 /// specified node are ISD::UNDEF.
112 } // end namespace ISD
552 // LSBaseSDNode => enum ISD::MemIndexedMode
553 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
554 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
565 uint16_t ExtTy : 2; // enum ISD::LoadExtType
650 /// are the opcode values in the ISD and <target>ISD namespaces. For
655 /// \<target\>ISD namespac
2613 namespace ISD { namespace in namespace:llvm
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp174 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
175 assert(ISD && "Invalid opcode");
193 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
194 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0},
195 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
196 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0},
197 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
198 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0},
199 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
200 {ISD
589 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
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H A DARMCallingConv.h21 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
24 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
27 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
30 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
33 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
39 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
42 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
45 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
48 CCValAssign::LocInfo LocInfo, ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp27 inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
31 case ISD::SETEQ:
33 case ISD::SETNE:
35 case ISD::SETLT:
37 case ISD::SETGT:
39 case ISD::SETLE:
41 case ISD::SETGE:
43 case ISD::SETULT:
45 case ISD::SETULE:
47 case ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h118 inline static AluCode isdToLanaiAluCode(ISD::NodeType Node_type) {
120 case ISD::ADD:
122 case ISD::ADDE:
124 case ISD::SUB:
126 case ISD::SUBE:
128 case ISD::AND:
130 case ISD::OR:
132 case ISD::XOR:
134 case ISD::SHL:
136 case ISD
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H A DLanaiISelLowering.cpp85 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::SETCC, MVT::i32, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
94 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
95 setOperationAction(ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.h20 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
24 ISD::ArgFlagsTy ArgFlags, CCState &State);
27 ISD::ArgFlagsTy ArgFlags, CCState &State);
30 ISD::ArgFlagsTy ArgFlags, CCState &State);
33 ISD::ArgFlagsTy ArgFlags, CCState &State);
36 ISD::ArgFlagsTy ArgFlags, CCState &State);
39 ISD::ArgFlagsTy ArgFlags, CCState &State);
41 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
44 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
48 ISD
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H A DAArch64TargetTransformInfo.cpp275 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
276 assert(ISD && "Invalid opcode");
313 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
314 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
315 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
316 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
319 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
320 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
321 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
322 { ISD
531 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
652 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
1011 int ISD = TLI->InstructionOpcodeToISD(Opcode); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp74 setOperationAction(ISD::LOAD, MVT::f32, Promote);
75 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
77 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
78 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
80 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
81 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
83 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
84 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
86 setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
87 AddPromotedToType(ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.h23 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
26 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
29 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
32 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
35 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
38 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
42 ISD::ArgFlagsTy ArgFlags, CCState &State);
H A DPPCCCState.cpp17 const SmallVectorImpl<ISD::OutputArg> &Outs) {
27 const SmallVectorImpl<ISD::InputArg> &Ins) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCCState.h32 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
37 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
42 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
49 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
52 PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
56 const SmallVectorImpl<ISD::InputArg> &Ins);
59 PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
75 /// See ISD::OutputArg::IsFixed,
89 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
104 void AnalyzeCallOperands(const SmallVectorImpl<ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp62 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
63 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
66 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
68 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
76 setOperationAction(ISD::SRA, MVT::i8, Custom);
77 setOperationAction(ISD::SHL, MVT::i8, Custom);
78 setOperationAction(ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp468 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
469 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
475 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
476 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
477 OP_TO_LIBCALL(ISD
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