Searched refs:HiHalf (Results 1 - 5 of 5) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAGHVX.cpp | 631 return OpRef(R.OpN & (Undef | Index | HiHalf)); 648 HiHalf = 0x40000000, 649 Whole = LoHalf | HiHalf, 724 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); 1011 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 1678 MachineInstr *HiHalf = local 1685 (void)HiHalf; 1686 LLVM_DEBUG(dbgs() << " "; HiHalf->dump(););
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H A D | SIInstrInfo.cpp | 5799 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); local 5811 Worklist.insert(&HiHalf); 5867 MachineInstr *HiHalf = local 5886 legalizeOperands(*HiHalf, MDT); 5936 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) local 5950 Worklist.insert(&HiHalf);
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H A D | SIISelLowering.cpp | 3860 MachineInstr *HiHalf = local 3874 TII->legalizeOperands(*HiHalf); 5262 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, local 5266 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); 5278 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 4839 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); local 4856 .addDef(HiHalf) 4864 .addUse(HiHalf);
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