Searched refs:EFX_STATIC_ASSERT (Results 1 - 25 of 25) sorted by relevance

/freebsd-13-stable/sys/dev/sfxge/common/
H A Dsiena_phy.c235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XF
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H A Def10_filter.c129 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST ==
131 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_HOST ==
133 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_MAC ==
135 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_PORT ==
137 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_MAC ==
139 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_PORT ==
141 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_ETHER_TYPE ==
143 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_INNER_VID ==
145 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_OUTER_VID ==
147 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IP_PROT
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H A Defx_nic.c343 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
345 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
347 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
349 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
351 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
353 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
355 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
357 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
647 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
649 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_I
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H A Def10_ev.c472 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
473 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
589 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
591 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
685 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
687 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
689 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
691 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
918 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
919 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TC
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H A Dmedford2_nic.c151 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
H A Dmedford_nic.c147 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
H A Def10_rx.c347 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
349 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
351 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
353 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
355 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
357 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
359 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
361 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
677 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
1033 EFX_STATIC_ASSERT(EFX_EV_RX_NLABEL
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H A Def10_phy.c47 EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN)
677 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <=
679 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <=
681 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <=
683 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <=
H A Defx_ev.c398 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
399 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
401 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
402 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
403 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
404 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
407 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
1312 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1313 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
H A Defx_port.c222 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) ==
H A Dhunt_nic.c226 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
H A Dsiena_nic.c98 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
449 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
763 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
777 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
H A Defx_tunnel.c120 EFX_STATIC_ASSERT(sizeof (efx_dword_t) ==
174 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
H A Defx_mcdi.c1513 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI);
1514 EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4);
1515 EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4);
1516 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP);
1517 EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS);
1518 EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T);
1519 EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS);
1680 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0);
1681 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0);
2348 EFX_STATIC_ASSERT(EFX_PHY_MEDIA_INFO_PAGE_SIZ
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H A Def10_image.c467 EFX_STATIC_ASSERT(sizeof (*header) == EFX_IMAGE_HEADER_SIZE);
468 EFX_STATIC_ASSERT(sizeof (*trailer) == EFX_IMAGE_TRAILER_SIZE);
736 EFX_STATIC_ASSERT(sizeof (chunk_hdr) == SIGNED_IMAGE_CHUNK_HDR_LEN);
H A Defx_vpd.c408 EFX_STATIC_ASSERT(TAG_NAME_END_DECODE == EFX_VPD_END);
409 EFX_STATIC_ASSERT(TAG_NAME_ID_STRING_DECODE == EFX_VPD_ID);
410 EFX_STATIC_ASSERT(TAG_NAME_VPD_R_DECODE == EFX_VPD_RO);
411 EFX_STATIC_ASSERT(TAG_NAME_VPD_W_DECODE == EFX_VPD_RW);
H A Defx_rx.c1340 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1341 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1610 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1615 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1616 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
H A Defx_tx.c947 EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS ==
952 EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
H A Def10_nic.c679 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
680 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
1264 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
H A Dmcdi_mon.c46 EFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field \
H A Dsiena_nvram.c355 EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0);
H A Dsiena_vpd.c91 EFX_STATIC_ASSERT(SIENA_MC_STATIC_CONFIG_VERSION == 0);
H A Defx_filter.c1327 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1383 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
H A Def10_nvram.c674 EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK);
1254 EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK);
H A Defx.h47 #define EFX_STATIC_ASSERT(_cond) \ macro

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