1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _SYS_EFX_H 36#define _SYS_EFX_H 37 38#include "efx_annote.h" 39#include "efsys.h" 40#include "efx_check.h" 41#include "efx_phy_ids.h" 42 43#ifdef __cplusplus 44extern "C" { 45#endif 46 47#define EFX_STATIC_ASSERT(_cond) \ 48 ((void)sizeof (char[(_cond) ? 1 : -1])) 49 50#define EFX_ARRAY_SIZE(_array) \ 51 (sizeof (_array) / sizeof ((_array)[0])) 52 53#define EFX_FIELD_OFFSET(_type, _field) \ 54 ((size_t)&(((_type *)0)->_field)) 55 56/* The macro expands divider twice */ 57#define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 58 59/* Round value up to the nearest power of two. */ 60#define EFX_P2ROUNDUP(_type, _value, _align) \ 61 (-(-(_type)(_value) & -(_type)(_align))) 62 63/* Align value down to the nearest power of two. */ 64#define EFX_P2ALIGN(_type, _value, _align) \ 65 ((_type)(_value) & -(_type)(_align)) 66 67/* Test if value is power of 2 aligned. */ 68#define EFX_IS_P2ALIGNED(_type, _value, _align) \ 69 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 70 71/* Return codes */ 72 73typedef __success(return == 0) int efx_rc_t; 74 75/* Chip families */ 76 77typedef enum efx_family_e { 78 EFX_FAMILY_INVALID, 79 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 80 EFX_FAMILY_SIENA, 81 EFX_FAMILY_HUNTINGTON, 82 EFX_FAMILY_MEDFORD, 83 EFX_FAMILY_MEDFORD2, 84 EFX_FAMILY_NTYPES 85} efx_family_t; 86 87extern __checkReturn efx_rc_t 88efx_family( 89 __in uint16_t venid, 90 __in uint16_t devid, 91 __out efx_family_t *efp, 92 __out unsigned int *membarp); 93 94#define EFX_PCI_VENID_SFC 0x1924 95 96#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 97 98#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 99#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 100#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 101 102#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 103#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 104#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 105 106#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 107#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 108 109#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 110#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 111#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 112 113#define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 114#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 115#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 116 117#define EFX_MEM_BAR_SIENA 2 118 119#define EFX_MEM_BAR_HUNTINGTON_PF 2 120#define EFX_MEM_BAR_HUNTINGTON_VF 0 121 122#define EFX_MEM_BAR_MEDFORD_PF 2 123#define EFX_MEM_BAR_MEDFORD_VF 0 124 125#define EFX_MEM_BAR_MEDFORD2 0 126 127/* Error codes */ 128 129enum { 130 EFX_ERR_INVALID, 131 EFX_ERR_SRAM_OOB, 132 EFX_ERR_BUFID_DC_OOB, 133 EFX_ERR_MEM_PERR, 134 EFX_ERR_RBUF_OWN, 135 EFX_ERR_TBUF_OWN, 136 EFX_ERR_RDESQ_OWN, 137 EFX_ERR_TDESQ_OWN, 138 EFX_ERR_EVQ_OWN, 139 EFX_ERR_EVFF_OFLO, 140 EFX_ERR_ILL_ADDR, 141 EFX_ERR_SRAM_PERR, 142 EFX_ERR_NCODES 143}; 144 145/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 146extern __checkReturn uint32_t 147efx_crc32_calculate( 148 __in uint32_t crc_init, 149 __in_ecount(length) uint8_t const *input, 150 __in int length); 151 152/* Type prototypes */ 153 154typedef struct efx_rxq_s efx_rxq_t; 155 156/* NIC */ 157 158typedef struct efx_nic_s efx_nic_t; 159 160extern __checkReturn efx_rc_t 161efx_nic_create( 162 __in efx_family_t family, 163 __in efsys_identifier_t *esip, 164 __in efsys_bar_t *esbp, 165 __in efsys_lock_t *eslp, 166 __deref_out efx_nic_t **enpp); 167 168/* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 169typedef enum efx_fw_variant_e { 170 EFX_FW_VARIANT_FULL_FEATURED, 171 EFX_FW_VARIANT_LOW_LATENCY, 172 EFX_FW_VARIANT_PACKED_STREAM, 173 EFX_FW_VARIANT_HIGH_TX_RATE, 174 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 175 EFX_FW_VARIANT_RULES_ENGINE, 176 EFX_FW_VARIANT_DPDK, 177 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 178} efx_fw_variant_t; 179 180extern __checkReturn efx_rc_t 181efx_nic_probe( 182 __in efx_nic_t *enp, 183 __in efx_fw_variant_t efv); 184 185extern __checkReturn efx_rc_t 186efx_nic_init( 187 __in efx_nic_t *enp); 188 189extern __checkReturn efx_rc_t 190efx_nic_reset( 191 __in efx_nic_t *enp); 192 193extern __checkReturn boolean_t 194efx_nic_hw_unavailable( 195 __in efx_nic_t *enp); 196 197extern void 198efx_nic_set_hw_unavailable( 199 __in efx_nic_t *enp); 200 201#if EFSYS_OPT_DIAG 202 203extern __checkReturn efx_rc_t 204efx_nic_register_test( 205 __in efx_nic_t *enp); 206 207#endif /* EFSYS_OPT_DIAG */ 208 209extern void 210efx_nic_fini( 211 __in efx_nic_t *enp); 212 213extern void 214efx_nic_unprobe( 215 __in efx_nic_t *enp); 216 217extern void 218efx_nic_destroy( 219 __in efx_nic_t *enp); 220 221#define EFX_PCIE_LINK_SPEED_GEN1 1 222#define EFX_PCIE_LINK_SPEED_GEN2 2 223#define EFX_PCIE_LINK_SPEED_GEN3 3 224 225typedef enum efx_pcie_link_performance_e { 226 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 227 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 228 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 229 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 230} efx_pcie_link_performance_t; 231 232extern __checkReturn efx_rc_t 233efx_nic_calculate_pcie_link_bandwidth( 234 __in uint32_t pcie_link_width, 235 __in uint32_t pcie_link_gen, 236 __out uint32_t *bandwidth_mbpsp); 237 238extern __checkReturn efx_rc_t 239efx_nic_check_pcie_link_speed( 240 __in efx_nic_t *enp, 241 __in uint32_t pcie_link_width, 242 __in uint32_t pcie_link_gen, 243 __out efx_pcie_link_performance_t *resultp); 244 245#if EFSYS_OPT_MCDI 246 247#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 248/* Huntington and Medford require MCDIv2 commands */ 249#define WITH_MCDI_V2 1 250#endif 251 252typedef struct efx_mcdi_req_s efx_mcdi_req_t; 253 254typedef enum efx_mcdi_exception_e { 255 EFX_MCDI_EXCEPTION_MC_REBOOT, 256 EFX_MCDI_EXCEPTION_MC_BADASSERT, 257} efx_mcdi_exception_t; 258 259#if EFSYS_OPT_MCDI_LOGGING 260typedef enum efx_log_msg_e { 261 EFX_LOG_INVALID, 262 EFX_LOG_MCDI_REQUEST, 263 EFX_LOG_MCDI_RESPONSE, 264} efx_log_msg_t; 265#endif /* EFSYS_OPT_MCDI_LOGGING */ 266 267typedef struct efx_mcdi_transport_s { 268 void *emt_context; 269 efsys_mem_t *emt_dma_mem; 270 void (*emt_execute)(void *, efx_mcdi_req_t *); 271 void (*emt_ev_cpl)(void *); 272 void (*emt_exception)(void *, efx_mcdi_exception_t); 273#if EFSYS_OPT_MCDI_LOGGING 274 void (*emt_logger)(void *, efx_log_msg_t, 275 void *, size_t, void *, size_t); 276#endif /* EFSYS_OPT_MCDI_LOGGING */ 277#if EFSYS_OPT_MCDI_PROXY_AUTH 278 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 279#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 280} efx_mcdi_transport_t; 281 282extern __checkReturn efx_rc_t 283efx_mcdi_init( 284 __in efx_nic_t *enp, 285 __in const efx_mcdi_transport_t *mtp); 286 287extern __checkReturn efx_rc_t 288efx_mcdi_reboot( 289 __in efx_nic_t *enp); 290 291 void 292efx_mcdi_new_epoch( 293 __in efx_nic_t *enp); 294 295extern void 296efx_mcdi_get_timeout( 297 __in efx_nic_t *enp, 298 __in efx_mcdi_req_t *emrp, 299 __out uint32_t *usec_timeoutp); 300 301extern void 302efx_mcdi_request_start( 303 __in efx_nic_t *enp, 304 __in efx_mcdi_req_t *emrp, 305 __in boolean_t ev_cpl); 306 307extern __checkReturn boolean_t 308efx_mcdi_request_poll( 309 __in efx_nic_t *enp); 310 311extern __checkReturn boolean_t 312efx_mcdi_request_abort( 313 __in efx_nic_t *enp); 314 315extern void 316efx_mcdi_fini( 317 __in efx_nic_t *enp); 318 319#endif /* EFSYS_OPT_MCDI */ 320 321/* INTR */ 322 323#define EFX_NINTR_SIENA 1024 324 325typedef enum efx_intr_type_e { 326 EFX_INTR_INVALID = 0, 327 EFX_INTR_LINE, 328 EFX_INTR_MESSAGE, 329 EFX_INTR_NTYPES 330} efx_intr_type_t; 331 332#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 333 334extern __checkReturn efx_rc_t 335efx_intr_init( 336 __in efx_nic_t *enp, 337 __in efx_intr_type_t type, 338 __in_opt efsys_mem_t *esmp); 339 340extern void 341efx_intr_enable( 342 __in efx_nic_t *enp); 343 344extern void 345efx_intr_disable( 346 __in efx_nic_t *enp); 347 348extern void 349efx_intr_disable_unlocked( 350 __in efx_nic_t *enp); 351 352#define EFX_INTR_NEVQS 32 353 354extern __checkReturn efx_rc_t 355efx_intr_trigger( 356 __in efx_nic_t *enp, 357 __in unsigned int level); 358 359extern void 360efx_intr_status_line( 361 __in efx_nic_t *enp, 362 __out boolean_t *fatalp, 363 __out uint32_t *maskp); 364 365extern void 366efx_intr_status_message( 367 __in efx_nic_t *enp, 368 __in unsigned int message, 369 __out boolean_t *fatalp); 370 371extern void 372efx_intr_fatal( 373 __in efx_nic_t *enp); 374 375extern void 376efx_intr_fini( 377 __in efx_nic_t *enp); 378 379/* MAC */ 380 381#if EFSYS_OPT_MAC_STATS 382 383/* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 384typedef enum efx_mac_stat_e { 385 EFX_MAC_RX_OCTETS, 386 EFX_MAC_RX_PKTS, 387 EFX_MAC_RX_UNICST_PKTS, 388 EFX_MAC_RX_MULTICST_PKTS, 389 EFX_MAC_RX_BRDCST_PKTS, 390 EFX_MAC_RX_PAUSE_PKTS, 391 EFX_MAC_RX_LE_64_PKTS, 392 EFX_MAC_RX_65_TO_127_PKTS, 393 EFX_MAC_RX_128_TO_255_PKTS, 394 EFX_MAC_RX_256_TO_511_PKTS, 395 EFX_MAC_RX_512_TO_1023_PKTS, 396 EFX_MAC_RX_1024_TO_15XX_PKTS, 397 EFX_MAC_RX_GE_15XX_PKTS, 398 EFX_MAC_RX_ERRORS, 399 EFX_MAC_RX_FCS_ERRORS, 400 EFX_MAC_RX_DROP_EVENTS, 401 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 402 EFX_MAC_RX_SYMBOL_ERRORS, 403 EFX_MAC_RX_ALIGN_ERRORS, 404 EFX_MAC_RX_INTERNAL_ERRORS, 405 EFX_MAC_RX_JABBER_PKTS, 406 EFX_MAC_RX_LANE0_CHAR_ERR, 407 EFX_MAC_RX_LANE1_CHAR_ERR, 408 EFX_MAC_RX_LANE2_CHAR_ERR, 409 EFX_MAC_RX_LANE3_CHAR_ERR, 410 EFX_MAC_RX_LANE0_DISP_ERR, 411 EFX_MAC_RX_LANE1_DISP_ERR, 412 EFX_MAC_RX_LANE2_DISP_ERR, 413 EFX_MAC_RX_LANE3_DISP_ERR, 414 EFX_MAC_RX_MATCH_FAULT, 415 EFX_MAC_RX_NODESC_DROP_CNT, 416 EFX_MAC_TX_OCTETS, 417 EFX_MAC_TX_PKTS, 418 EFX_MAC_TX_UNICST_PKTS, 419 EFX_MAC_TX_MULTICST_PKTS, 420 EFX_MAC_TX_BRDCST_PKTS, 421 EFX_MAC_TX_PAUSE_PKTS, 422 EFX_MAC_TX_LE_64_PKTS, 423 EFX_MAC_TX_65_TO_127_PKTS, 424 EFX_MAC_TX_128_TO_255_PKTS, 425 EFX_MAC_TX_256_TO_511_PKTS, 426 EFX_MAC_TX_512_TO_1023_PKTS, 427 EFX_MAC_TX_1024_TO_15XX_PKTS, 428 EFX_MAC_TX_GE_15XX_PKTS, 429 EFX_MAC_TX_ERRORS, 430 EFX_MAC_TX_SGL_COL_PKTS, 431 EFX_MAC_TX_MULT_COL_PKTS, 432 EFX_MAC_TX_EX_COL_PKTS, 433 EFX_MAC_TX_LATE_COL_PKTS, 434 EFX_MAC_TX_DEF_PKTS, 435 EFX_MAC_TX_EX_DEF_PKTS, 436 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 437 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 438 EFX_MAC_PM_TRUNC_VFIFO_FULL, 439 EFX_MAC_PM_DISCARD_VFIFO_FULL, 440 EFX_MAC_PM_TRUNC_QBB, 441 EFX_MAC_PM_DISCARD_QBB, 442 EFX_MAC_PM_DISCARD_MAPPING, 443 EFX_MAC_RXDP_Q_DISABLED_PKTS, 444 EFX_MAC_RXDP_DI_DROPPED_PKTS, 445 EFX_MAC_RXDP_STREAMING_PKTS, 446 EFX_MAC_RXDP_HLB_FETCH, 447 EFX_MAC_RXDP_HLB_WAIT, 448 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 449 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 450 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 451 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 452 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 453 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 454 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 455 EFX_MAC_VADAPTER_RX_BAD_BYTES, 456 EFX_MAC_VADAPTER_RX_OVERFLOW, 457 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 458 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 459 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 460 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 461 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 462 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 463 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 464 EFX_MAC_VADAPTER_TX_BAD_BYTES, 465 EFX_MAC_VADAPTER_TX_OVERFLOW, 466 EFX_MAC_FEC_UNCORRECTED_ERRORS, 467 EFX_MAC_FEC_CORRECTED_ERRORS, 468 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 469 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 470 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 471 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 472 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 473 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 474 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 475 EFX_MAC_CTPIO_OVERFLOW_FAIL, 476 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 477 EFX_MAC_CTPIO_TIMEOUT_FAIL, 478 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 479 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 480 EFX_MAC_CTPIO_INVALID_WR_FAIL, 481 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 482 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 483 EFX_MAC_CTPIO_RUNT_FALLBACK, 484 EFX_MAC_CTPIO_SUCCESS, 485 EFX_MAC_CTPIO_FALLBACK, 486 EFX_MAC_CTPIO_POISON, 487 EFX_MAC_CTPIO_ERASE, 488 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 489 EFX_MAC_RXDP_HLB_IDLE, 490 EFX_MAC_RXDP_HLB_TIMEOUT, 491 EFX_MAC_NSTATS 492} efx_mac_stat_t; 493 494/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 495 496#endif /* EFSYS_OPT_MAC_STATS */ 497 498typedef enum efx_link_mode_e { 499 EFX_LINK_UNKNOWN = 0, 500 EFX_LINK_DOWN, 501 EFX_LINK_10HDX, 502 EFX_LINK_10FDX, 503 EFX_LINK_100HDX, 504 EFX_LINK_100FDX, 505 EFX_LINK_1000HDX, 506 EFX_LINK_1000FDX, 507 EFX_LINK_10000FDX, 508 EFX_LINK_40000FDX, 509 EFX_LINK_25000FDX, 510 EFX_LINK_50000FDX, 511 EFX_LINK_100000FDX, 512 EFX_LINK_NMODES 513} efx_link_mode_t; 514 515#define EFX_MAC_ADDR_LEN 6 516 517#define EFX_VNI_OR_VSID_LEN 3 518 519#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 520 521#define EFX_MAC_MULTICAST_LIST_MAX 256 522 523#define EFX_MAC_SDU_MAX 9202 524 525#define EFX_MAC_PDU_ADJUSTMENT \ 526 (/* EtherII */ 14 \ 527 + /* VLAN */ 4 \ 528 + /* CRC */ 4 \ 529 + /* bug16011 */ 16) \ 530 531#define EFX_MAC_PDU(_sdu) \ 532 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 533 534/* 535 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 536 * the SDU rounded up slightly. 537 */ 538#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 539 540#define EFX_MAC_PDU_MIN 60 541#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 542 543extern __checkReturn efx_rc_t 544efx_mac_pdu_get( 545 __in efx_nic_t *enp, 546 __out size_t *pdu); 547 548extern __checkReturn efx_rc_t 549efx_mac_pdu_set( 550 __in efx_nic_t *enp, 551 __in size_t pdu); 552 553extern __checkReturn efx_rc_t 554efx_mac_addr_set( 555 __in efx_nic_t *enp, 556 __in uint8_t *addr); 557 558extern __checkReturn efx_rc_t 559efx_mac_filter_set( 560 __in efx_nic_t *enp, 561 __in boolean_t all_unicst, 562 __in boolean_t mulcst, 563 __in boolean_t all_mulcst, 564 __in boolean_t brdcst); 565 566extern __checkReturn efx_rc_t 567efx_mac_multicast_list_set( 568 __in efx_nic_t *enp, 569 __in_ecount(6*count) uint8_t const *addrs, 570 __in int count); 571 572extern __checkReturn efx_rc_t 573efx_mac_filter_default_rxq_set( 574 __in efx_nic_t *enp, 575 __in efx_rxq_t *erp, 576 __in boolean_t using_rss); 577 578extern void 579efx_mac_filter_default_rxq_clear( 580 __in efx_nic_t *enp); 581 582extern __checkReturn efx_rc_t 583efx_mac_drain( 584 __in efx_nic_t *enp, 585 __in boolean_t enabled); 586 587extern __checkReturn efx_rc_t 588efx_mac_up( 589 __in efx_nic_t *enp, 590 __out boolean_t *mac_upp); 591 592#define EFX_FCNTL_RESPOND 0x00000001 593#define EFX_FCNTL_GENERATE 0x00000002 594 595extern __checkReturn efx_rc_t 596efx_mac_fcntl_set( 597 __in efx_nic_t *enp, 598 __in unsigned int fcntl, 599 __in boolean_t autoneg); 600 601extern void 602efx_mac_fcntl_get( 603 __in efx_nic_t *enp, 604 __out unsigned int *fcntl_wantedp, 605 __out unsigned int *fcntl_linkp); 606 607#if EFSYS_OPT_MAC_STATS 608 609#if EFSYS_OPT_NAMES 610 611extern __checkReturn const char * 612efx_mac_stat_name( 613 __in efx_nic_t *enp, 614 __in unsigned int id); 615 616#endif /* EFSYS_OPT_NAMES */ 617 618#define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 619 620#define EFX_MAC_STATS_MASK_NPAGES \ 621 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 622 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 623 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 624 625/* 626 * Get mask of MAC statistics supported by the hardware. 627 * 628 * If mask_size is insufficient to return the mask, EINVAL error is 629 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 630 * (which is sizeof (uint32_t)) is sufficient. 631 */ 632extern __checkReturn efx_rc_t 633efx_mac_stats_get_mask( 634 __in efx_nic_t *enp, 635 __out_bcount(mask_size) uint32_t *maskp, 636 __in size_t mask_size); 637 638#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 639 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 640 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 641 642extern __checkReturn efx_rc_t 643efx_mac_stats_clear( 644 __in efx_nic_t *enp); 645 646/* 647 * Upload mac statistics supported by the hardware into the given buffer. 648 * 649 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 650 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 651 * 652 * The hardware will only DMA statistics that it understands (of course). 653 * Drivers should not make any assumptions about which statistics are 654 * supported, especially when the statistics are generated by firmware. 655 * 656 * Thus, drivers should zero this buffer before use, so that not-understood 657 * statistics read back as zero. 658 */ 659extern __checkReturn efx_rc_t 660efx_mac_stats_upload( 661 __in efx_nic_t *enp, 662 __in efsys_mem_t *esmp); 663 664extern __checkReturn efx_rc_t 665efx_mac_stats_periodic( 666 __in efx_nic_t *enp, 667 __in efsys_mem_t *esmp, 668 __in uint16_t period_ms, 669 __in boolean_t events); 670 671extern __checkReturn efx_rc_t 672efx_mac_stats_update( 673 __in efx_nic_t *enp, 674 __in efsys_mem_t *esmp, 675 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 676 __inout_opt uint32_t *generationp); 677 678#endif /* EFSYS_OPT_MAC_STATS */ 679 680/* MON */ 681 682typedef enum efx_mon_type_e { 683 EFX_MON_INVALID = 0, 684 EFX_MON_SFC90X0, 685 EFX_MON_SFC91X0, 686 EFX_MON_SFC92X0, 687 EFX_MON_NTYPES 688} efx_mon_type_t; 689 690#if EFSYS_OPT_NAMES 691 692extern const char * 693efx_mon_name( 694 __in efx_nic_t *enp); 695 696#endif /* EFSYS_OPT_NAMES */ 697 698extern __checkReturn efx_rc_t 699efx_mon_init( 700 __in efx_nic_t *enp); 701 702#if EFSYS_OPT_MON_STATS 703 704#define EFX_MON_STATS_PAGE_SIZE 0x100 705#define EFX_MON_MASK_ELEMENT_SIZE 32 706 707/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 708typedef enum efx_mon_stat_e { 709 EFX_MON_STAT_CONTROLLER_TEMP, 710 EFX_MON_STAT_PHY_COMMON_TEMP, 711 EFX_MON_STAT_CONTROLLER_COOLING, 712 EFX_MON_STAT_PHY0_TEMP, 713 EFX_MON_STAT_PHY0_COOLING, 714 EFX_MON_STAT_PHY1_TEMP, 715 EFX_MON_STAT_PHY1_COOLING, 716 EFX_MON_STAT_IN_1V0, 717 EFX_MON_STAT_IN_1V2, 718 EFX_MON_STAT_IN_1V8, 719 EFX_MON_STAT_IN_2V5, 720 EFX_MON_STAT_IN_3V3, 721 EFX_MON_STAT_IN_12V0, 722 EFX_MON_STAT_IN_1V2A, 723 EFX_MON_STAT_IN_VREF, 724 EFX_MON_STAT_OUT_VAOE, 725 EFX_MON_STAT_AOE_TEMP, 726 EFX_MON_STAT_PSU_AOE_TEMP, 727 EFX_MON_STAT_PSU_TEMP, 728 EFX_MON_STAT_FAN_0, 729 EFX_MON_STAT_FAN_1, 730 EFX_MON_STAT_FAN_2, 731 EFX_MON_STAT_FAN_3, 732 EFX_MON_STAT_FAN_4, 733 EFX_MON_STAT_IN_VAOE, 734 EFX_MON_STAT_OUT_IAOE, 735 EFX_MON_STAT_IN_IAOE, 736 EFX_MON_STAT_NIC_POWER, 737 EFX_MON_STAT_IN_0V9, 738 EFX_MON_STAT_IN_I0V9, 739 EFX_MON_STAT_IN_I1V2, 740 EFX_MON_STAT_IN_0V9_ADC, 741 EFX_MON_STAT_CONTROLLER_2_TEMP, 742 EFX_MON_STAT_VREG_INTERNAL_TEMP, 743 EFX_MON_STAT_VREG_0V9_TEMP, 744 EFX_MON_STAT_VREG_1V2_TEMP, 745 EFX_MON_STAT_CONTROLLER_VPTAT, 746 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 747 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 748 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 749 EFX_MON_STAT_AMBIENT_TEMP, 750 EFX_MON_STAT_AIRFLOW, 751 EFX_MON_STAT_VDD08D_VSS08D_CSR, 752 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 753 EFX_MON_STAT_HOTPOINT_TEMP, 754 EFX_MON_STAT_PHY_POWER_PORT0, 755 EFX_MON_STAT_PHY_POWER_PORT1, 756 EFX_MON_STAT_MUM_VCC, 757 EFX_MON_STAT_IN_0V9_A, 758 EFX_MON_STAT_IN_I0V9_A, 759 EFX_MON_STAT_VREG_0V9_A_TEMP, 760 EFX_MON_STAT_IN_0V9_B, 761 EFX_MON_STAT_IN_I0V9_B, 762 EFX_MON_STAT_VREG_0V9_B_TEMP, 763 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 764 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 765 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 766 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 767 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 768 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 769 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 770 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 771 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 772 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 773 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 774 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 775 EFX_MON_STAT_SODIMM_VOUT, 776 EFX_MON_STAT_SODIMM_0_TEMP, 777 EFX_MON_STAT_SODIMM_1_TEMP, 778 EFX_MON_STAT_PHY0_VCC, 779 EFX_MON_STAT_PHY1_VCC, 780 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 781 EFX_MON_STAT_BOARD_FRONT_TEMP, 782 EFX_MON_STAT_BOARD_BACK_TEMP, 783 EFX_MON_STAT_IN_I1V8, 784 EFX_MON_STAT_IN_I2V5, 785 EFX_MON_STAT_IN_I3V3, 786 EFX_MON_STAT_IN_I12V0, 787 EFX_MON_STAT_IN_1V3, 788 EFX_MON_STAT_IN_I1V3, 789 EFX_MON_NSTATS 790} efx_mon_stat_t; 791 792/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 793 794typedef enum efx_mon_stat_state_e { 795 EFX_MON_STAT_STATE_OK = 0, 796 EFX_MON_STAT_STATE_WARNING = 1, 797 EFX_MON_STAT_STATE_FATAL = 2, 798 EFX_MON_STAT_STATE_BROKEN = 3, 799 EFX_MON_STAT_STATE_NO_READING = 4, 800} efx_mon_stat_state_t; 801 802typedef enum efx_mon_stat_unit_e { 803 EFX_MON_STAT_UNIT_UNKNOWN = 0, 804 EFX_MON_STAT_UNIT_BOOL, 805 EFX_MON_STAT_UNIT_TEMP_C, 806 EFX_MON_STAT_UNIT_VOLTAGE_MV, 807 EFX_MON_STAT_UNIT_CURRENT_MA, 808 EFX_MON_STAT_UNIT_POWER_W, 809 EFX_MON_STAT_UNIT_RPM, 810 EFX_MON_NUNITS 811} efx_mon_stat_unit_t; 812 813typedef struct efx_mon_stat_value_s { 814 uint16_t emsv_value; 815 efx_mon_stat_state_t emsv_state; 816 efx_mon_stat_unit_t emsv_unit; 817} efx_mon_stat_value_t; 818 819typedef struct efx_mon_limit_value_s { 820 uint16_t emlv_warning_min; 821 uint16_t emlv_warning_max; 822 uint16_t emlv_fatal_min; 823 uint16_t emlv_fatal_max; 824} efx_mon_stat_limits_t; 825 826typedef enum efx_mon_stat_portmask_e { 827 EFX_MON_STAT_PORTMAP_NONE = 0, 828 EFX_MON_STAT_PORTMAP_PORT0 = 1, 829 EFX_MON_STAT_PORTMAP_PORT1 = 2, 830 EFX_MON_STAT_PORTMAP_PORT2 = 3, 831 EFX_MON_STAT_PORTMAP_PORT3 = 4, 832 EFX_MON_STAT_PORTMAP_ALL = (-1), 833 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 834} efx_mon_stat_portmask_t; 835 836#if EFSYS_OPT_NAMES 837 838extern const char * 839efx_mon_stat_name( 840 __in efx_nic_t *enp, 841 __in efx_mon_stat_t id); 842 843extern const char * 844efx_mon_stat_description( 845 __in efx_nic_t *enp, 846 __in efx_mon_stat_t id); 847 848#endif /* EFSYS_OPT_NAMES */ 849 850extern __checkReturn boolean_t 851efx_mon_mcdi_to_efx_stat( 852 __in int mcdi_index, 853 __out efx_mon_stat_t *statp); 854 855extern __checkReturn boolean_t 856efx_mon_get_stat_unit( 857 __in efx_mon_stat_t stat, 858 __out efx_mon_stat_unit_t *unitp); 859 860extern __checkReturn boolean_t 861efx_mon_get_stat_portmap( 862 __in efx_mon_stat_t stat, 863 __out efx_mon_stat_portmask_t *maskp); 864 865extern __checkReturn efx_rc_t 866efx_mon_stats_update( 867 __in efx_nic_t *enp, 868 __in efsys_mem_t *esmp, 869 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 870 871extern __checkReturn efx_rc_t 872efx_mon_limits_update( 873 __in efx_nic_t *enp, 874 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 875 876#endif /* EFSYS_OPT_MON_STATS */ 877 878extern void 879efx_mon_fini( 880 __in efx_nic_t *enp); 881 882/* PHY */ 883 884extern __checkReturn efx_rc_t 885efx_phy_verify( 886 __in efx_nic_t *enp); 887 888#if EFSYS_OPT_PHY_LED_CONTROL 889 890typedef enum efx_phy_led_mode_e { 891 EFX_PHY_LED_DEFAULT = 0, 892 EFX_PHY_LED_OFF, 893 EFX_PHY_LED_ON, 894 EFX_PHY_LED_FLASH, 895 EFX_PHY_LED_NMODES 896} efx_phy_led_mode_t; 897 898extern __checkReturn efx_rc_t 899efx_phy_led_set( 900 __in efx_nic_t *enp, 901 __in efx_phy_led_mode_t mode); 902 903#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 904 905extern __checkReturn efx_rc_t 906efx_port_init( 907 __in efx_nic_t *enp); 908 909#if EFSYS_OPT_LOOPBACK 910 911typedef enum efx_loopback_type_e { 912 EFX_LOOPBACK_OFF = 0, 913 EFX_LOOPBACK_DATA = 1, 914 EFX_LOOPBACK_GMAC = 2, 915 EFX_LOOPBACK_XGMII = 3, 916 EFX_LOOPBACK_XGXS = 4, 917 EFX_LOOPBACK_XAUI = 5, 918 EFX_LOOPBACK_GMII = 6, 919 EFX_LOOPBACK_SGMII = 7, 920 EFX_LOOPBACK_XGBR = 8, 921 EFX_LOOPBACK_XFI = 9, 922 EFX_LOOPBACK_XAUI_FAR = 10, 923 EFX_LOOPBACK_GMII_FAR = 11, 924 EFX_LOOPBACK_SGMII_FAR = 12, 925 EFX_LOOPBACK_XFI_FAR = 13, 926 EFX_LOOPBACK_GPHY = 14, 927 EFX_LOOPBACK_PHY_XS = 15, 928 EFX_LOOPBACK_PCS = 16, 929 EFX_LOOPBACK_PMA_PMD = 17, 930 EFX_LOOPBACK_XPORT = 18, 931 EFX_LOOPBACK_XGMII_WS = 19, 932 EFX_LOOPBACK_XAUI_WS = 20, 933 EFX_LOOPBACK_XAUI_WS_FAR = 21, 934 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 935 EFX_LOOPBACK_GMII_WS = 23, 936 EFX_LOOPBACK_XFI_WS = 24, 937 EFX_LOOPBACK_XFI_WS_FAR = 25, 938 EFX_LOOPBACK_PHYXS_WS = 26, 939 EFX_LOOPBACK_PMA_INT = 27, 940 EFX_LOOPBACK_SD_NEAR = 28, 941 EFX_LOOPBACK_SD_FAR = 29, 942 EFX_LOOPBACK_PMA_INT_WS = 30, 943 EFX_LOOPBACK_SD_FEP2_WS = 31, 944 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 945 EFX_LOOPBACK_SD_FEP_WS = 33, 946 EFX_LOOPBACK_SD_FES_WS = 34, 947 EFX_LOOPBACK_AOE_INT_NEAR = 35, 948 EFX_LOOPBACK_DATA_WS = 36, 949 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 950 EFX_LOOPBACK_NTYPES 951} efx_loopback_type_t; 952 953typedef enum efx_loopback_kind_e { 954 EFX_LOOPBACK_KIND_OFF = 0, 955 EFX_LOOPBACK_KIND_ALL, 956 EFX_LOOPBACK_KIND_MAC, 957 EFX_LOOPBACK_KIND_PHY, 958 EFX_LOOPBACK_NKINDS 959} efx_loopback_kind_t; 960 961extern void 962efx_loopback_mask( 963 __in efx_loopback_kind_t loopback_kind, 964 __out efx_qword_t *maskp); 965 966extern __checkReturn efx_rc_t 967efx_port_loopback_set( 968 __in efx_nic_t *enp, 969 __in efx_link_mode_t link_mode, 970 __in efx_loopback_type_t type); 971 972#if EFSYS_OPT_NAMES 973 974extern __checkReturn const char * 975efx_loopback_type_name( 976 __in efx_nic_t *enp, 977 __in efx_loopback_type_t type); 978 979#endif /* EFSYS_OPT_NAMES */ 980 981#endif /* EFSYS_OPT_LOOPBACK */ 982 983extern __checkReturn efx_rc_t 984efx_port_poll( 985 __in efx_nic_t *enp, 986 __out_opt efx_link_mode_t *link_modep); 987 988extern void 989efx_port_fini( 990 __in efx_nic_t *enp); 991 992typedef enum efx_phy_cap_type_e { 993 EFX_PHY_CAP_INVALID = 0, 994 EFX_PHY_CAP_10HDX, 995 EFX_PHY_CAP_10FDX, 996 EFX_PHY_CAP_100HDX, 997 EFX_PHY_CAP_100FDX, 998 EFX_PHY_CAP_1000HDX, 999 EFX_PHY_CAP_1000FDX, 1000 EFX_PHY_CAP_10000FDX, 1001 EFX_PHY_CAP_PAUSE, 1002 EFX_PHY_CAP_ASYM, 1003 EFX_PHY_CAP_AN, 1004 EFX_PHY_CAP_40000FDX, 1005 EFX_PHY_CAP_DDM, 1006 EFX_PHY_CAP_100000FDX, 1007 EFX_PHY_CAP_25000FDX, 1008 EFX_PHY_CAP_50000FDX, 1009 EFX_PHY_CAP_BASER_FEC, 1010 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1011 EFX_PHY_CAP_RS_FEC, 1012 EFX_PHY_CAP_RS_FEC_REQUESTED, 1013 EFX_PHY_CAP_25G_BASER_FEC, 1014 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1015 EFX_PHY_CAP_NTYPES 1016} efx_phy_cap_type_t; 1017 1018#define EFX_PHY_CAP_CURRENT 0x00000000 1019#define EFX_PHY_CAP_DEFAULT 0x00000001 1020#define EFX_PHY_CAP_PERM 0x00000002 1021 1022extern void 1023efx_phy_adv_cap_get( 1024 __in efx_nic_t *enp, 1025 __in uint32_t flag, 1026 __out uint32_t *maskp); 1027 1028extern __checkReturn efx_rc_t 1029efx_phy_adv_cap_set( 1030 __in efx_nic_t *enp, 1031 __in uint32_t mask); 1032 1033extern void 1034efx_phy_lp_cap_get( 1035 __in efx_nic_t *enp, 1036 __out uint32_t *maskp); 1037 1038extern __checkReturn efx_rc_t 1039efx_phy_oui_get( 1040 __in efx_nic_t *enp, 1041 __out uint32_t *ouip); 1042 1043typedef enum efx_phy_media_type_e { 1044 EFX_PHY_MEDIA_INVALID = 0, 1045 EFX_PHY_MEDIA_XAUI, 1046 EFX_PHY_MEDIA_CX4, 1047 EFX_PHY_MEDIA_KX4, 1048 EFX_PHY_MEDIA_XFP, 1049 EFX_PHY_MEDIA_SFP_PLUS, 1050 EFX_PHY_MEDIA_BASE_T, 1051 EFX_PHY_MEDIA_QSFP_PLUS, 1052 EFX_PHY_MEDIA_NTYPES 1053} efx_phy_media_type_t; 1054 1055/* 1056 * Get the type of medium currently used. If the board has ports for 1057 * modules, a module is present, and we recognise the media type of 1058 * the module, then this will be the media type of the module. 1059 * Otherwise it will be the media type of the port. 1060 */ 1061extern void 1062efx_phy_media_type_get( 1063 __in efx_nic_t *enp, 1064 __out efx_phy_media_type_t *typep); 1065 1066/* 1067 * 2-wire device address of the base information in accordance with SFF-8472 1068 * Diagnostic Monitoring Interface for Optical Transceivers section 1069 * 4 Memory Organization. 1070 */ 1071#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1072 1073/* 1074 * 2-wire device address of the digital diagnostics monitoring interface 1075 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1076 * Transceivers section 4 Memory Organization. 1077 */ 1078#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1079 1080/* 1081 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1082 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1083 * Operation. 1084 */ 1085#define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1086 1087/* 1088 * Maximum accessible data offset for PHY module information. 1089 */ 1090#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1091 1092extern __checkReturn efx_rc_t 1093efx_phy_module_get_info( 1094 __in efx_nic_t *enp, 1095 __in uint8_t dev_addr, 1096 __in size_t offset, 1097 __in size_t len, 1098 __out_bcount(len) uint8_t *data); 1099 1100#if EFSYS_OPT_PHY_STATS 1101 1102/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1103typedef enum efx_phy_stat_e { 1104 EFX_PHY_STAT_OUI, 1105 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1106 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1107 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1108 EFX_PHY_STAT_PMA_PMD_REV_A, 1109 EFX_PHY_STAT_PMA_PMD_REV_B, 1110 EFX_PHY_STAT_PMA_PMD_REV_C, 1111 EFX_PHY_STAT_PMA_PMD_REV_D, 1112 EFX_PHY_STAT_PCS_LINK_UP, 1113 EFX_PHY_STAT_PCS_RX_FAULT, 1114 EFX_PHY_STAT_PCS_TX_FAULT, 1115 EFX_PHY_STAT_PCS_BER, 1116 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1117 EFX_PHY_STAT_PHY_XS_LINK_UP, 1118 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1119 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1120 EFX_PHY_STAT_PHY_XS_ALIGN, 1121 EFX_PHY_STAT_PHY_XS_SYNC_A, 1122 EFX_PHY_STAT_PHY_XS_SYNC_B, 1123 EFX_PHY_STAT_PHY_XS_SYNC_C, 1124 EFX_PHY_STAT_PHY_XS_SYNC_D, 1125 EFX_PHY_STAT_AN_LINK_UP, 1126 EFX_PHY_STAT_AN_MASTER, 1127 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1128 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1129 EFX_PHY_STAT_CL22EXT_LINK_UP, 1130 EFX_PHY_STAT_SNR_A, 1131 EFX_PHY_STAT_SNR_B, 1132 EFX_PHY_STAT_SNR_C, 1133 EFX_PHY_STAT_SNR_D, 1134 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1135 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1136 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1137 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1138 EFX_PHY_STAT_AN_COMPLETE, 1139 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1140 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1141 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1142 EFX_PHY_STAT_PCS_FW_VERSION_0, 1143 EFX_PHY_STAT_PCS_FW_VERSION_1, 1144 EFX_PHY_STAT_PCS_FW_VERSION_2, 1145 EFX_PHY_STAT_PCS_FW_VERSION_3, 1146 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1147 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1148 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1149 EFX_PHY_STAT_PCS_OP_MODE, 1150 EFX_PHY_NSTATS 1151} efx_phy_stat_t; 1152 1153/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1154 1155#if EFSYS_OPT_NAMES 1156 1157extern const char * 1158efx_phy_stat_name( 1159 __in efx_nic_t *enp, 1160 __in efx_phy_stat_t stat); 1161 1162#endif /* EFSYS_OPT_NAMES */ 1163 1164#define EFX_PHY_STATS_SIZE 0x100 1165 1166extern __checkReturn efx_rc_t 1167efx_phy_stats_update( 1168 __in efx_nic_t *enp, 1169 __in efsys_mem_t *esmp, 1170 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1171 1172#endif /* EFSYS_OPT_PHY_STATS */ 1173 1174#if EFSYS_OPT_BIST 1175 1176typedef enum efx_bist_type_e { 1177 EFX_BIST_TYPE_UNKNOWN, 1178 EFX_BIST_TYPE_PHY_NORMAL, 1179 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1180 EFX_BIST_TYPE_PHY_CABLE_LONG, 1181 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1182 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1183 EFX_BIST_TYPE_REG, /* Test the register memories */ 1184 EFX_BIST_TYPE_NTYPES, 1185} efx_bist_type_t; 1186 1187typedef enum efx_bist_result_e { 1188 EFX_BIST_RESULT_UNKNOWN, 1189 EFX_BIST_RESULT_RUNNING, 1190 EFX_BIST_RESULT_PASSED, 1191 EFX_BIST_RESULT_FAILED, 1192} efx_bist_result_t; 1193 1194typedef enum efx_phy_cable_status_e { 1195 EFX_PHY_CABLE_STATUS_OK, 1196 EFX_PHY_CABLE_STATUS_INVALID, 1197 EFX_PHY_CABLE_STATUS_OPEN, 1198 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1199 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1200 EFX_PHY_CABLE_STATUS_BUSY, 1201} efx_phy_cable_status_t; 1202 1203typedef enum efx_bist_value_e { 1204 EFX_BIST_PHY_CABLE_LENGTH_A, 1205 EFX_BIST_PHY_CABLE_LENGTH_B, 1206 EFX_BIST_PHY_CABLE_LENGTH_C, 1207 EFX_BIST_PHY_CABLE_LENGTH_D, 1208 EFX_BIST_PHY_CABLE_STATUS_A, 1209 EFX_BIST_PHY_CABLE_STATUS_B, 1210 EFX_BIST_PHY_CABLE_STATUS_C, 1211 EFX_BIST_PHY_CABLE_STATUS_D, 1212 EFX_BIST_FAULT_CODE, 1213 /* 1214 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1215 * response. 1216 */ 1217 EFX_BIST_MEM_TEST, 1218 EFX_BIST_MEM_ADDR, 1219 EFX_BIST_MEM_BUS, 1220 EFX_BIST_MEM_EXPECT, 1221 EFX_BIST_MEM_ACTUAL, 1222 EFX_BIST_MEM_ECC, 1223 EFX_BIST_MEM_ECC_PARITY, 1224 EFX_BIST_MEM_ECC_FATAL, 1225 EFX_BIST_NVALUES, 1226} efx_bist_value_t; 1227 1228extern __checkReturn efx_rc_t 1229efx_bist_enable_offline( 1230 __in efx_nic_t *enp); 1231 1232extern __checkReturn efx_rc_t 1233efx_bist_start( 1234 __in efx_nic_t *enp, 1235 __in efx_bist_type_t type); 1236 1237extern __checkReturn efx_rc_t 1238efx_bist_poll( 1239 __in efx_nic_t *enp, 1240 __in efx_bist_type_t type, 1241 __out efx_bist_result_t *resultp, 1242 __out_opt uint32_t *value_maskp, 1243 __out_ecount_opt(count) unsigned long *valuesp, 1244 __in size_t count); 1245 1246extern void 1247efx_bist_stop( 1248 __in efx_nic_t *enp, 1249 __in efx_bist_type_t type); 1250 1251#endif /* EFSYS_OPT_BIST */ 1252 1253#define EFX_FEATURE_IPV6 0x00000001 1254#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1255#define EFX_FEATURE_LINK_EVENTS 0x00000004 1256#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1257#define EFX_FEATURE_MCDI 0x00000020 1258#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1259#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1260#define EFX_FEATURE_TURBO 0x00000100 1261#define EFX_FEATURE_MCDI_DMA 0x00000200 1262#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1263#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1264#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1265#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1266#define EFX_FEATURE_PACKED_STREAM 0x00004000 1267#define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1268 1269typedef enum efx_tunnel_protocol_e { 1270 EFX_TUNNEL_PROTOCOL_NONE = 0, 1271 EFX_TUNNEL_PROTOCOL_VXLAN, 1272 EFX_TUNNEL_PROTOCOL_GENEVE, 1273 EFX_TUNNEL_PROTOCOL_NVGRE, 1274 EFX_TUNNEL_NPROTOS 1275} efx_tunnel_protocol_t; 1276 1277typedef enum efx_vi_window_shift_e { 1278 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1279 EFX_VI_WINDOW_SHIFT_8K = 13, 1280 EFX_VI_WINDOW_SHIFT_16K = 14, 1281 EFX_VI_WINDOW_SHIFT_64K = 16, 1282} efx_vi_window_shift_t; 1283 1284typedef struct efx_nic_cfg_s { 1285 uint32_t enc_board_type; 1286 uint32_t enc_phy_type; 1287#if EFSYS_OPT_NAMES 1288 char enc_phy_name[21]; 1289#endif 1290 char enc_phy_revision[21]; 1291 efx_mon_type_t enc_mon_type; 1292#if EFSYS_OPT_MON_STATS 1293 uint32_t enc_mon_stat_dma_buf_size; 1294 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1295#endif 1296 unsigned int enc_features; 1297 efx_vi_window_shift_t enc_vi_window_shift; 1298 uint8_t enc_mac_addr[6]; 1299 uint8_t enc_port; /* PHY port number */ 1300 uint32_t enc_intr_vec_base; 1301 uint32_t enc_intr_limit; 1302 uint32_t enc_evq_limit; 1303 uint32_t enc_txq_limit; 1304 uint32_t enc_rxq_limit; 1305 uint32_t enc_txq_max_ndescs; 1306 uint32_t enc_buftbl_limit; 1307 uint32_t enc_piobuf_limit; 1308 uint32_t enc_piobuf_size; 1309 uint32_t enc_piobuf_min_alloc_size; 1310 uint32_t enc_evq_timer_quantum_ns; 1311 uint32_t enc_evq_timer_max_us; 1312 uint32_t enc_clk_mult; 1313 uint32_t enc_rx_prefix_size; 1314 uint32_t enc_rx_buf_align_start; 1315 uint32_t enc_rx_buf_align_end; 1316#if EFSYS_OPT_RX_SCALE 1317 uint32_t enc_rx_scale_max_exclusive_contexts; 1318 /* 1319 * Mask of supported hash algorithms. 1320 * Hash algorithm types are used as the bit indices. 1321 */ 1322 uint32_t enc_rx_scale_hash_alg_mask; 1323 /* 1324 * Indicates whether port numbers can be included to the 1325 * input data for hash computation. 1326 */ 1327 boolean_t enc_rx_scale_l4_hash_supported; 1328 boolean_t enc_rx_scale_additional_modes_supported; 1329#endif /* EFSYS_OPT_RX_SCALE */ 1330#if EFSYS_OPT_LOOPBACK 1331 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1332#endif /* EFSYS_OPT_LOOPBACK */ 1333#if EFSYS_OPT_PHY_FLAGS 1334 uint32_t enc_phy_flags_mask; 1335#endif /* EFSYS_OPT_PHY_FLAGS */ 1336#if EFSYS_OPT_PHY_LED_CONTROL 1337 uint32_t enc_led_mask; 1338#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1339#if EFSYS_OPT_PHY_STATS 1340 uint64_t enc_phy_stat_mask; 1341#endif /* EFSYS_OPT_PHY_STATS */ 1342#if EFSYS_OPT_MCDI 1343 uint8_t enc_mcdi_mdio_channel; 1344#if EFSYS_OPT_PHY_STATS 1345 uint32_t enc_mcdi_phy_stat_mask; 1346#endif /* EFSYS_OPT_PHY_STATS */ 1347#if EFSYS_OPT_MON_STATS 1348 uint32_t *enc_mcdi_sensor_maskp; 1349 uint32_t enc_mcdi_sensor_mask_size; 1350#endif /* EFSYS_OPT_MON_STATS */ 1351#endif /* EFSYS_OPT_MCDI */ 1352#if EFSYS_OPT_BIST 1353 uint32_t enc_bist_mask; 1354#endif /* EFSYS_OPT_BIST */ 1355#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 1356 uint32_t enc_pf; 1357 uint32_t enc_vf; 1358 uint32_t enc_privilege_mask; 1359#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 1360 boolean_t enc_bug26807_workaround; 1361 boolean_t enc_bug35388_workaround; 1362 boolean_t enc_bug41750_workaround; 1363 boolean_t enc_bug61265_workaround; 1364 boolean_t enc_bug61297_workaround; 1365 boolean_t enc_rx_batching_enabled; 1366 /* Maximum number of descriptors completed in an rx event. */ 1367 uint32_t enc_rx_batch_max; 1368 /* Number of rx descriptors the hardware requires for a push. */ 1369 uint32_t enc_rx_push_align; 1370 /* Maximum amount of data in DMA descriptor */ 1371 uint32_t enc_tx_dma_desc_size_max; 1372 /* 1373 * Boundary which DMA descriptor data must not cross or 0 if no 1374 * limitation. 1375 */ 1376 uint32_t enc_tx_dma_desc_boundary; 1377 /* 1378 * Maximum number of bytes into the packet the TCP header can start for 1379 * the hardware to apply TSO packet edits. 1380 */ 1381 uint32_t enc_tx_tso_tcp_header_offset_limit; 1382 boolean_t enc_fw_assisted_tso_enabled; 1383 boolean_t enc_fw_assisted_tso_v2_enabled; 1384 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1385 /* Number of TSO contexts on the NIC (FATSOv2) */ 1386 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1387 boolean_t enc_hw_tx_insert_vlan_enabled; 1388 /* Number of PFs on the NIC */ 1389 uint32_t enc_hw_pf_count; 1390 /* Datapath firmware vadapter/vport/vswitch support */ 1391 boolean_t enc_datapath_cap_evb; 1392 boolean_t enc_rx_disable_scatter_supported; 1393 boolean_t enc_allow_set_mac_with_installed_filters; 1394 boolean_t enc_enhanced_set_mac_supported; 1395 boolean_t enc_init_evq_v2_supported; 1396 boolean_t enc_rx_packed_stream_supported; 1397 boolean_t enc_rx_var_packed_stream_supported; 1398 boolean_t enc_rx_es_super_buffer_supported; 1399 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1400 boolean_t enc_pm_and_rxdp_counters; 1401 boolean_t enc_mac_stats_40g_tx_size_bins; 1402 uint32_t enc_tunnel_encapsulations_supported; 1403 /* 1404 * NIC global maximum for unique UDP tunnel ports shared by all 1405 * functions. 1406 */ 1407 uint32_t enc_tunnel_config_udp_entries_max; 1408 /* External port identifier */ 1409 uint8_t enc_external_port; 1410 uint32_t enc_mcdi_max_payload_length; 1411 /* VPD may be per-PF or global */ 1412 boolean_t enc_vpd_is_global; 1413 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1414 uint32_t enc_required_pcie_bandwidth_mbps; 1415 uint32_t enc_max_pcie_link_gen; 1416 /* Firmware verifies integrity of NVRAM updates */ 1417 uint32_t enc_nvram_update_verify_result_supported; 1418 /* Firmware support for extended MAC_STATS buffer */ 1419 uint32_t enc_mac_stats_nstats; 1420 boolean_t enc_fec_counters; 1421 boolean_t enc_hlb_counters; 1422 /* Firmware support for "FLAG" and "MARK" filter actions */ 1423 boolean_t enc_filter_action_flag_supported; 1424 boolean_t enc_filter_action_mark_supported; 1425 uint32_t enc_filter_action_mark_max; 1426} efx_nic_cfg_t; 1427 1428#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1429#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1430 1431#define EFX_PCI_FUNCTION(_encp) \ 1432 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1433 1434#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1435 1436extern const efx_nic_cfg_t * 1437efx_nic_cfg_get( 1438 __in efx_nic_t *enp); 1439 1440/* RxDPCPU firmware id values by which FW variant can be identified */ 1441#define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1442#define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1443#define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1444#define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1445#define EFX_RXDP_DPDK_FW_ID 0x6 1446 1447typedef struct efx_nic_fw_info_s { 1448 /* Basic FW version information */ 1449 uint16_t enfi_mc_fw_version[4]; 1450 /* 1451 * If datapath capabilities can be detected, 1452 * additional FW information is to be shown 1453 */ 1454 boolean_t enfi_dpcpu_fw_ids_valid; 1455 /* Rx and Tx datapath CPU FW IDs */ 1456 uint16_t enfi_rx_dpcpu_fw_id; 1457 uint16_t enfi_tx_dpcpu_fw_id; 1458} efx_nic_fw_info_t; 1459 1460extern __checkReturn efx_rc_t 1461efx_nic_get_fw_version( 1462 __in efx_nic_t *enp, 1463 __out efx_nic_fw_info_t *enfip); 1464 1465/* Driver resource limits (minimum required/maximum usable). */ 1466typedef struct efx_drv_limits_s { 1467 uint32_t edl_min_evq_count; 1468 uint32_t edl_max_evq_count; 1469 1470 uint32_t edl_min_rxq_count; 1471 uint32_t edl_max_rxq_count; 1472 1473 uint32_t edl_min_txq_count; 1474 uint32_t edl_max_txq_count; 1475 1476 /* PIO blocks (sub-allocated from piobuf) */ 1477 uint32_t edl_min_pio_alloc_size; 1478 uint32_t edl_max_pio_alloc_count; 1479} efx_drv_limits_t; 1480 1481extern __checkReturn efx_rc_t 1482efx_nic_set_drv_limits( 1483 __inout efx_nic_t *enp, 1484 __in efx_drv_limits_t *edlp); 1485 1486typedef enum efx_nic_region_e { 1487 EFX_REGION_VI, /* Memory BAR UC mapping */ 1488 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1489} efx_nic_region_t; 1490 1491extern __checkReturn efx_rc_t 1492efx_nic_get_bar_region( 1493 __in efx_nic_t *enp, 1494 __in efx_nic_region_t region, 1495 __out uint32_t *offsetp, 1496 __out size_t *sizep); 1497 1498extern __checkReturn efx_rc_t 1499efx_nic_get_vi_pool( 1500 __in efx_nic_t *enp, 1501 __out uint32_t *evq_countp, 1502 __out uint32_t *rxq_countp, 1503 __out uint32_t *txq_countp); 1504 1505#if EFSYS_OPT_VPD 1506 1507typedef enum efx_vpd_tag_e { 1508 EFX_VPD_ID = 0x02, 1509 EFX_VPD_END = 0x0f, 1510 EFX_VPD_RO = 0x10, 1511 EFX_VPD_RW = 0x11, 1512} efx_vpd_tag_t; 1513 1514typedef uint16_t efx_vpd_keyword_t; 1515 1516typedef struct efx_vpd_value_s { 1517 efx_vpd_tag_t evv_tag; 1518 efx_vpd_keyword_t evv_keyword; 1519 uint8_t evv_length; 1520 uint8_t evv_value[0x100]; 1521} efx_vpd_value_t; 1522 1523#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1524 1525extern __checkReturn efx_rc_t 1526efx_vpd_init( 1527 __in efx_nic_t *enp); 1528 1529extern __checkReturn efx_rc_t 1530efx_vpd_size( 1531 __in efx_nic_t *enp, 1532 __out size_t *sizep); 1533 1534extern __checkReturn efx_rc_t 1535efx_vpd_read( 1536 __in efx_nic_t *enp, 1537 __out_bcount(size) caddr_t data, 1538 __in size_t size); 1539 1540extern __checkReturn efx_rc_t 1541efx_vpd_verify( 1542 __in efx_nic_t *enp, 1543 __in_bcount(size) caddr_t data, 1544 __in size_t size); 1545 1546extern __checkReturn efx_rc_t 1547efx_vpd_reinit( 1548 __in efx_nic_t *enp, 1549 __in_bcount(size) caddr_t data, 1550 __in size_t size); 1551 1552extern __checkReturn efx_rc_t 1553efx_vpd_get( 1554 __in efx_nic_t *enp, 1555 __in_bcount(size) caddr_t data, 1556 __in size_t size, 1557 __inout efx_vpd_value_t *evvp); 1558 1559extern __checkReturn efx_rc_t 1560efx_vpd_set( 1561 __in efx_nic_t *enp, 1562 __inout_bcount(size) caddr_t data, 1563 __in size_t size, 1564 __in efx_vpd_value_t *evvp); 1565 1566extern __checkReturn efx_rc_t 1567efx_vpd_next( 1568 __in efx_nic_t *enp, 1569 __inout_bcount(size) caddr_t data, 1570 __in size_t size, 1571 __out efx_vpd_value_t *evvp, 1572 __inout unsigned int *contp); 1573 1574extern __checkReturn efx_rc_t 1575efx_vpd_write( 1576 __in efx_nic_t *enp, 1577 __in_bcount(size) caddr_t data, 1578 __in size_t size); 1579 1580extern void 1581efx_vpd_fini( 1582 __in efx_nic_t *enp); 1583 1584#endif /* EFSYS_OPT_VPD */ 1585 1586/* NVRAM */ 1587 1588#if EFSYS_OPT_NVRAM 1589 1590typedef enum efx_nvram_type_e { 1591 EFX_NVRAM_INVALID = 0, 1592 EFX_NVRAM_BOOTROM, 1593 EFX_NVRAM_BOOTROM_CFG, 1594 EFX_NVRAM_MC_FIRMWARE, 1595 EFX_NVRAM_MC_GOLDEN, 1596 EFX_NVRAM_PHY, 1597 EFX_NVRAM_NULLPHY, 1598 EFX_NVRAM_FPGA, 1599 EFX_NVRAM_FCFW, 1600 EFX_NVRAM_CPLD, 1601 EFX_NVRAM_FPGA_BACKUP, 1602 EFX_NVRAM_DYNAMIC_CFG, 1603 EFX_NVRAM_LICENSE, 1604 EFX_NVRAM_UEFIROM, 1605 EFX_NVRAM_MUM_FIRMWARE, 1606 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1607 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1608 EFX_NVRAM_NTYPES, 1609} efx_nvram_type_t; 1610 1611extern __checkReturn efx_rc_t 1612efx_nvram_init( 1613 __in efx_nic_t *enp); 1614 1615#if EFSYS_OPT_DIAG 1616 1617extern __checkReturn efx_rc_t 1618efx_nvram_test( 1619 __in efx_nic_t *enp); 1620 1621#endif /* EFSYS_OPT_DIAG */ 1622 1623extern __checkReturn efx_rc_t 1624efx_nvram_size( 1625 __in efx_nic_t *enp, 1626 __in efx_nvram_type_t type, 1627 __out size_t *sizep); 1628 1629extern __checkReturn efx_rc_t 1630efx_nvram_rw_start( 1631 __in efx_nic_t *enp, 1632 __in efx_nvram_type_t type, 1633 __out_opt size_t *pref_chunkp); 1634 1635extern __checkReturn efx_rc_t 1636efx_nvram_rw_finish( 1637 __in efx_nic_t *enp, 1638 __in efx_nvram_type_t type, 1639 __out_opt uint32_t *verify_resultp); 1640 1641extern __checkReturn efx_rc_t 1642efx_nvram_get_version( 1643 __in efx_nic_t *enp, 1644 __in efx_nvram_type_t type, 1645 __out uint32_t *subtypep, 1646 __out_ecount(4) uint16_t version[4]); 1647 1648extern __checkReturn efx_rc_t 1649efx_nvram_read_chunk( 1650 __in efx_nic_t *enp, 1651 __in efx_nvram_type_t type, 1652 __in unsigned int offset, 1653 __out_bcount(size) caddr_t data, 1654 __in size_t size); 1655 1656extern __checkReturn efx_rc_t 1657efx_nvram_read_backup( 1658 __in efx_nic_t *enp, 1659 __in efx_nvram_type_t type, 1660 __in unsigned int offset, 1661 __out_bcount(size) caddr_t data, 1662 __in size_t size); 1663 1664extern __checkReturn efx_rc_t 1665efx_nvram_set_version( 1666 __in efx_nic_t *enp, 1667 __in efx_nvram_type_t type, 1668 __in_ecount(4) uint16_t version[4]); 1669 1670extern __checkReturn efx_rc_t 1671efx_nvram_validate( 1672 __in efx_nic_t *enp, 1673 __in efx_nvram_type_t type, 1674 __in_bcount(partn_size) caddr_t partn_data, 1675 __in size_t partn_size); 1676 1677extern __checkReturn efx_rc_t 1678efx_nvram_erase( 1679 __in efx_nic_t *enp, 1680 __in efx_nvram_type_t type); 1681 1682extern __checkReturn efx_rc_t 1683efx_nvram_write_chunk( 1684 __in efx_nic_t *enp, 1685 __in efx_nvram_type_t type, 1686 __in unsigned int offset, 1687 __in_bcount(size) caddr_t data, 1688 __in size_t size); 1689 1690extern void 1691efx_nvram_fini( 1692 __in efx_nic_t *enp); 1693 1694#endif /* EFSYS_OPT_NVRAM */ 1695 1696#if EFSYS_OPT_BOOTCFG 1697 1698/* Report size and offset of bootcfg sector in NVRAM partition. */ 1699extern __checkReturn efx_rc_t 1700efx_bootcfg_sector_info( 1701 __in efx_nic_t *enp, 1702 __in uint32_t pf, 1703 __out_opt uint32_t *sector_countp, 1704 __out size_t *offsetp, 1705 __out size_t *max_sizep); 1706 1707/* 1708 * Copy bootcfg sector data to a target buffer which may differ in size. 1709 * Optionally corrects format errors in source buffer. 1710 */ 1711extern efx_rc_t 1712efx_bootcfg_copy_sector( 1713 __in efx_nic_t *enp, 1714 __inout_bcount(sector_length) 1715 uint8_t *sector, 1716 __in size_t sector_length, 1717 __out_bcount(data_size) uint8_t *data, 1718 __in size_t data_size, 1719 __in boolean_t handle_format_errors); 1720 1721extern efx_rc_t 1722efx_bootcfg_read( 1723 __in efx_nic_t *enp, 1724 __out_bcount(size) uint8_t *data, 1725 __in size_t size); 1726 1727extern efx_rc_t 1728efx_bootcfg_write( 1729 __in efx_nic_t *enp, 1730 __in_bcount(size) uint8_t *data, 1731 __in size_t size); 1732 1733/* 1734 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1735 * (see https://tools.ietf.org/html/rfc1533) 1736 * 1737 * Summarising the format: the buffer is a sequence of options. All options 1738 * begin with a tag octet, which uniquely identifies the option. Fixed- 1739 * length options without data consist of only a tag octet. Only options PAD 1740 * (0) and END (255) are fixed length. All other options are variable-length 1741 * with a length octet following the tag octet. The value of the length 1742 * octet does not include the two octets specifying the tag and length. The 1743 * length octet is followed by "length" octets of data. 1744 * 1745 * Option data may be a sequence of sub-options in the same format. The data 1746 * content of the encapsulating option is one or more encapsulated sub-options, 1747 * with no terminating END tag is required. 1748 * 1749 * To be valid, the top-level sequence of options should be terminated by an 1750 * END tag. The buffer should be padded with the PAD byte. 1751 * 1752 * When stored to NVRAM, the DHCP option format buffer is preceded by a 1753 * checksum octet. The full buffer (including after the END tag) contributes 1754 * to the checksum, hence the need to fill the buffer to the end with PAD. 1755 */ 1756 1757#define EFX_DHCP_END ((uint8_t)0xff) 1758#define EFX_DHCP_PAD ((uint8_t)0) 1759 1760#define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 1761 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 1762 1763extern __checkReturn uint8_t 1764efx_dhcp_csum( 1765 __in_bcount(size) uint8_t const *data, 1766 __in size_t size); 1767 1768extern __checkReturn efx_rc_t 1769efx_dhcp_verify( 1770 __in_bcount(size) uint8_t const *data, 1771 __in size_t size, 1772 __out_opt size_t *usedp); 1773 1774extern __checkReturn efx_rc_t 1775efx_dhcp_find_tag( 1776 __in_bcount(buffer_length) uint8_t *bufferp, 1777 __in size_t buffer_length, 1778 __in uint16_t opt, 1779 __deref_out uint8_t **valuepp, 1780 __out size_t *value_lengthp); 1781 1782extern __checkReturn efx_rc_t 1783efx_dhcp_find_end( 1784 __in_bcount(buffer_length) uint8_t *bufferp, 1785 __in size_t buffer_length, 1786 __deref_out uint8_t **endpp); 1787 1788extern __checkReturn efx_rc_t 1789efx_dhcp_delete_tag( 1790 __inout_bcount(buffer_length) uint8_t *bufferp, 1791 __in size_t buffer_length, 1792 __in uint16_t opt); 1793 1794extern __checkReturn efx_rc_t 1795efx_dhcp_add_tag( 1796 __inout_bcount(buffer_length) uint8_t *bufferp, 1797 __in size_t buffer_length, 1798 __in uint16_t opt, 1799 __in_bcount_opt(value_length) uint8_t *valuep, 1800 __in size_t value_length); 1801 1802extern __checkReturn efx_rc_t 1803efx_dhcp_update_tag( 1804 __inout_bcount(buffer_length) uint8_t *bufferp, 1805 __in size_t buffer_length, 1806 __in uint16_t opt, 1807 __in uint8_t *value_locationp, 1808 __in_bcount_opt(value_length) uint8_t *valuep, 1809 __in size_t value_length); 1810 1811#endif /* EFSYS_OPT_BOOTCFG */ 1812 1813#if EFSYS_OPT_IMAGE_LAYOUT 1814 1815#include "ef10_signed_image_layout.h" 1816 1817/* 1818 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 1819 * 1820 * NOTE: 1821 * The image header format is extensible. However, older drivers require an 1822 * exact match of image header version and header length when validating and 1823 * writing firmware images. 1824 * 1825 * To avoid breaking backward compatibility, we use the upper bits of the 1826 * controller version fields to contain an extra version number used for 1827 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 1828 * version). See bug39254 and SF-102785-PS for details. 1829 */ 1830typedef struct efx_image_header_s { 1831 uint32_t eih_magic; 1832 uint32_t eih_version; 1833 uint32_t eih_type; 1834 uint32_t eih_subtype; 1835 uint32_t eih_code_size; 1836 uint32_t eih_size; 1837 union { 1838 uint32_t eih_controller_version_min; 1839 struct { 1840 uint16_t eih_controller_version_min_short; 1841 uint8_t eih_extra_version_a; 1842 uint8_t eih_extra_version_b; 1843 }; 1844 }; 1845 union { 1846 uint32_t eih_controller_version_max; 1847 struct { 1848 uint16_t eih_controller_version_max_short; 1849 uint8_t eih_extra_version_c; 1850 uint8_t eih_extra_version_d; 1851 }; 1852 }; 1853 uint16_t eih_code_version_a; 1854 uint16_t eih_code_version_b; 1855 uint16_t eih_code_version_c; 1856 uint16_t eih_code_version_d; 1857} efx_image_header_t; 1858 1859#define EFX_IMAGE_HEADER_SIZE (40) 1860#define EFX_IMAGE_HEADER_VERSION (4) 1861#define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 1862 1863typedef struct efx_image_trailer_s { 1864 uint32_t eit_crc; 1865} efx_image_trailer_t; 1866 1867#define EFX_IMAGE_TRAILER_SIZE (4) 1868 1869typedef enum efx_image_format_e { 1870 EFX_IMAGE_FORMAT_NO_IMAGE, 1871 EFX_IMAGE_FORMAT_INVALID, 1872 EFX_IMAGE_FORMAT_UNSIGNED, 1873 EFX_IMAGE_FORMAT_SIGNED, 1874} efx_image_format_t; 1875 1876typedef struct efx_image_info_s { 1877 efx_image_format_t eii_format; 1878 uint8_t * eii_imagep; 1879 size_t eii_image_size; 1880 efx_image_header_t * eii_headerp; 1881} efx_image_info_t; 1882 1883extern __checkReturn efx_rc_t 1884efx_check_reflash_image( 1885 __in void *bufferp, 1886 __in uint32_t buffer_size, 1887 __out efx_image_info_t *infop); 1888 1889extern __checkReturn efx_rc_t 1890efx_build_signed_image_write_buffer( 1891 __out_bcount(buffer_size) 1892 uint8_t *bufferp, 1893 __in uint32_t buffer_size, 1894 __in efx_image_info_t *infop, 1895 __out efx_image_header_t **headerpp); 1896 1897#endif /* EFSYS_OPT_IMAGE_LAYOUT */ 1898 1899#if EFSYS_OPT_DIAG 1900 1901typedef enum efx_pattern_type_t { 1902 EFX_PATTERN_BYTE_INCREMENT = 0, 1903 EFX_PATTERN_ALL_THE_SAME, 1904 EFX_PATTERN_BIT_ALTERNATE, 1905 EFX_PATTERN_BYTE_ALTERNATE, 1906 EFX_PATTERN_BYTE_CHANGING, 1907 EFX_PATTERN_BIT_SWEEP, 1908 EFX_PATTERN_NTYPES 1909} efx_pattern_type_t; 1910 1911typedef void 1912(*efx_sram_pattern_fn_t)( 1913 __in size_t row, 1914 __in boolean_t negate, 1915 __out efx_qword_t *eqp); 1916 1917extern __checkReturn efx_rc_t 1918efx_sram_test( 1919 __in efx_nic_t *enp, 1920 __in efx_pattern_type_t type); 1921 1922#endif /* EFSYS_OPT_DIAG */ 1923 1924extern __checkReturn efx_rc_t 1925efx_sram_buf_tbl_set( 1926 __in efx_nic_t *enp, 1927 __in uint32_t id, 1928 __in efsys_mem_t *esmp, 1929 __in size_t n); 1930 1931extern void 1932efx_sram_buf_tbl_clear( 1933 __in efx_nic_t *enp, 1934 __in uint32_t id, 1935 __in size_t n); 1936 1937#define EFX_BUF_TBL_SIZE 0x20000 1938 1939#define EFX_BUF_SIZE 4096 1940 1941/* EV */ 1942 1943typedef struct efx_evq_s efx_evq_t; 1944 1945#if EFSYS_OPT_QSTATS 1946 1947/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1948typedef enum efx_ev_qstat_e { 1949 EV_ALL, 1950 EV_RX, 1951 EV_RX_OK, 1952 EV_RX_FRM_TRUNC, 1953 EV_RX_TOBE_DISC, 1954 EV_RX_PAUSE_FRM_ERR, 1955 EV_RX_BUF_OWNER_ID_ERR, 1956 EV_RX_IPV4_HDR_CHKSUM_ERR, 1957 EV_RX_TCP_UDP_CHKSUM_ERR, 1958 EV_RX_ETH_CRC_ERR, 1959 EV_RX_IP_FRAG_ERR, 1960 EV_RX_MCAST_PKT, 1961 EV_RX_MCAST_HASH_MATCH, 1962 EV_RX_TCP_IPV4, 1963 EV_RX_TCP_IPV6, 1964 EV_RX_UDP_IPV4, 1965 EV_RX_UDP_IPV6, 1966 EV_RX_OTHER_IPV4, 1967 EV_RX_OTHER_IPV6, 1968 EV_RX_NON_IP, 1969 EV_RX_BATCH, 1970 EV_TX, 1971 EV_TX_WQ_FF_FULL, 1972 EV_TX_PKT_ERR, 1973 EV_TX_PKT_TOO_BIG, 1974 EV_TX_UNEXPECTED, 1975 EV_GLOBAL, 1976 EV_GLOBAL_MNT, 1977 EV_DRIVER, 1978 EV_DRIVER_SRM_UPD_DONE, 1979 EV_DRIVER_TX_DESCQ_FLS_DONE, 1980 EV_DRIVER_RX_DESCQ_FLS_DONE, 1981 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1982 EV_DRIVER_RX_DSC_ERROR, 1983 EV_DRIVER_TX_DSC_ERROR, 1984 EV_DRV_GEN, 1985 EV_MCDI_RESPONSE, 1986 EV_NQSTATS 1987} efx_ev_qstat_t; 1988 1989/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1990 1991#endif /* EFSYS_OPT_QSTATS */ 1992 1993extern __checkReturn efx_rc_t 1994efx_ev_init( 1995 __in efx_nic_t *enp); 1996 1997extern void 1998efx_ev_fini( 1999 __in efx_nic_t *enp); 2000 2001#define EFX_EVQ_MAXNEVS 32768 2002#define EFX_EVQ_MINNEVS 512 2003 2004#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 2005#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 2006 2007#define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2008#define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2009#define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2010#define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2011 2012#define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2013#define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2014#define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2015 2016extern __checkReturn efx_rc_t 2017efx_ev_qcreate( 2018 __in efx_nic_t *enp, 2019 __in unsigned int index, 2020 __in efsys_mem_t *esmp, 2021 __in size_t ndescs, 2022 __in uint32_t id, 2023 __in uint32_t us, 2024 __in uint32_t flags, 2025 __deref_out efx_evq_t **eepp); 2026 2027extern void 2028efx_ev_qpost( 2029 __in efx_evq_t *eep, 2030 __in uint16_t data); 2031 2032typedef __checkReturn boolean_t 2033(*efx_initialized_ev_t)( 2034 __in_opt void *arg); 2035 2036#define EFX_PKT_UNICAST 0x0004 2037#define EFX_PKT_START 0x0008 2038 2039#define EFX_PKT_VLAN_TAGGED 0x0010 2040#define EFX_CKSUM_TCPUDP 0x0020 2041#define EFX_CKSUM_IPV4 0x0040 2042#define EFX_PKT_CONT 0x0080 2043 2044#define EFX_CHECK_VLAN 0x0100 2045#define EFX_PKT_TCP 0x0200 2046#define EFX_PKT_UDP 0x0400 2047#define EFX_PKT_IPV4 0x0800 2048 2049#define EFX_PKT_IPV6 0x1000 2050#define EFX_PKT_PREFIX_LEN 0x2000 2051#define EFX_ADDR_MISMATCH 0x4000 2052#define EFX_DISCARD 0x8000 2053 2054/* 2055 * The following flags are used only for packed stream 2056 * mode. The values for the flags are reused to fit into 16 bit, 2057 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2058 * packed stream mode 2059 */ 2060#define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2061#define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2062 2063#define EFX_EV_RX_NLABELS 32 2064#define EFX_EV_TX_NLABELS 32 2065 2066typedef __checkReturn boolean_t 2067(*efx_rx_ev_t)( 2068 __in_opt void *arg, 2069 __in uint32_t label, 2070 __in uint32_t id, 2071 __in uint32_t size, 2072 __in uint16_t flags); 2073 2074#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2075 2076/* 2077 * Packed stream mode is documented in SF-112241-TC. 2078 * The general idea is that, instead of putting each incoming 2079 * packet into a separate buffer which is specified in a RX 2080 * descriptor, a large buffer is provided to the hardware and 2081 * packets are put there in a continuous stream. 2082 * The main advantage of such an approach is that RX queue refilling 2083 * happens much less frequently. 2084 * 2085 * Equal stride packed stream mode is documented in SF-119419-TC. 2086 * The general idea is to utilize advantages of the packed stream, 2087 * but avoid indirection in packets representation. 2088 * The main advantage of such an approach is that RX queue refilling 2089 * happens much less frequently and packets buffers are independent 2090 * from upper layers point of view. 2091 */ 2092 2093typedef __checkReturn boolean_t 2094(*efx_rx_ps_ev_t)( 2095 __in_opt void *arg, 2096 __in uint32_t label, 2097 __in uint32_t id, 2098 __in uint32_t pkt_count, 2099 __in uint16_t flags); 2100 2101#endif 2102 2103typedef __checkReturn boolean_t 2104(*efx_tx_ev_t)( 2105 __in_opt void *arg, 2106 __in uint32_t label, 2107 __in uint32_t id); 2108 2109#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2110#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2111#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2112#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2113#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2114#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2115#define EFX_EXCEPTION_RX_ERROR 0x00000007 2116#define EFX_EXCEPTION_TX_ERROR 0x00000008 2117#define EFX_EXCEPTION_EV_ERROR 0x00000009 2118 2119typedef __checkReturn boolean_t 2120(*efx_exception_ev_t)( 2121 __in_opt void *arg, 2122 __in uint32_t label, 2123 __in uint32_t data); 2124 2125typedef __checkReturn boolean_t 2126(*efx_rxq_flush_done_ev_t)( 2127 __in_opt void *arg, 2128 __in uint32_t rxq_index); 2129 2130typedef __checkReturn boolean_t 2131(*efx_rxq_flush_failed_ev_t)( 2132 __in_opt void *arg, 2133 __in uint32_t rxq_index); 2134 2135typedef __checkReturn boolean_t 2136(*efx_txq_flush_done_ev_t)( 2137 __in_opt void *arg, 2138 __in uint32_t txq_index); 2139 2140typedef __checkReturn boolean_t 2141(*efx_software_ev_t)( 2142 __in_opt void *arg, 2143 __in uint16_t magic); 2144 2145typedef __checkReturn boolean_t 2146(*efx_sram_ev_t)( 2147 __in_opt void *arg, 2148 __in uint32_t code); 2149 2150#define EFX_SRAM_CLEAR 0 2151#define EFX_SRAM_UPDATE 1 2152#define EFX_SRAM_ILLEGAL_CLEAR 2 2153 2154typedef __checkReturn boolean_t 2155(*efx_wake_up_ev_t)( 2156 __in_opt void *arg, 2157 __in uint32_t label); 2158 2159typedef __checkReturn boolean_t 2160(*efx_timer_ev_t)( 2161 __in_opt void *arg, 2162 __in uint32_t label); 2163 2164typedef __checkReturn boolean_t 2165(*efx_link_change_ev_t)( 2166 __in_opt void *arg, 2167 __in efx_link_mode_t link_mode); 2168 2169#if EFSYS_OPT_MON_STATS 2170 2171typedef __checkReturn boolean_t 2172(*efx_monitor_ev_t)( 2173 __in_opt void *arg, 2174 __in efx_mon_stat_t id, 2175 __in efx_mon_stat_value_t value); 2176 2177#endif /* EFSYS_OPT_MON_STATS */ 2178 2179#if EFSYS_OPT_MAC_STATS 2180 2181typedef __checkReturn boolean_t 2182(*efx_mac_stats_ev_t)( 2183 __in_opt void *arg, 2184 __in uint32_t generation); 2185 2186#endif /* EFSYS_OPT_MAC_STATS */ 2187 2188typedef struct efx_ev_callbacks_s { 2189 efx_initialized_ev_t eec_initialized; 2190 efx_rx_ev_t eec_rx; 2191#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2192 efx_rx_ps_ev_t eec_rx_ps; 2193#endif 2194 efx_tx_ev_t eec_tx; 2195 efx_exception_ev_t eec_exception; 2196 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2197 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2198 efx_txq_flush_done_ev_t eec_txq_flush_done; 2199 efx_software_ev_t eec_software; 2200 efx_sram_ev_t eec_sram; 2201 efx_wake_up_ev_t eec_wake_up; 2202 efx_timer_ev_t eec_timer; 2203 efx_link_change_ev_t eec_link_change; 2204#if EFSYS_OPT_MON_STATS 2205 efx_monitor_ev_t eec_monitor; 2206#endif /* EFSYS_OPT_MON_STATS */ 2207#if EFSYS_OPT_MAC_STATS 2208 efx_mac_stats_ev_t eec_mac_stats; 2209#endif /* EFSYS_OPT_MAC_STATS */ 2210} efx_ev_callbacks_t; 2211 2212extern __checkReturn boolean_t 2213efx_ev_qpending( 2214 __in efx_evq_t *eep, 2215 __in unsigned int count); 2216 2217#if EFSYS_OPT_EV_PREFETCH 2218 2219extern void 2220efx_ev_qprefetch( 2221 __in efx_evq_t *eep, 2222 __in unsigned int count); 2223 2224#endif /* EFSYS_OPT_EV_PREFETCH */ 2225 2226extern void 2227efx_ev_qpoll( 2228 __in efx_evq_t *eep, 2229 __inout unsigned int *countp, 2230 __in const efx_ev_callbacks_t *eecp, 2231 __in_opt void *arg); 2232 2233extern __checkReturn efx_rc_t 2234efx_ev_usecs_to_ticks( 2235 __in efx_nic_t *enp, 2236 __in unsigned int usecs, 2237 __out unsigned int *ticksp); 2238 2239extern __checkReturn efx_rc_t 2240efx_ev_qmoderate( 2241 __in efx_evq_t *eep, 2242 __in unsigned int us); 2243 2244extern __checkReturn efx_rc_t 2245efx_ev_qprime( 2246 __in efx_evq_t *eep, 2247 __in unsigned int count); 2248 2249#if EFSYS_OPT_QSTATS 2250 2251#if EFSYS_OPT_NAMES 2252 2253extern const char * 2254efx_ev_qstat_name( 2255 __in efx_nic_t *enp, 2256 __in unsigned int id); 2257 2258#endif /* EFSYS_OPT_NAMES */ 2259 2260extern void 2261efx_ev_qstats_update( 2262 __in efx_evq_t *eep, 2263 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2264 2265#endif /* EFSYS_OPT_QSTATS */ 2266 2267extern void 2268efx_ev_qdestroy( 2269 __in efx_evq_t *eep); 2270 2271/* RX */ 2272 2273extern __checkReturn efx_rc_t 2274efx_rx_init( 2275 __inout efx_nic_t *enp); 2276 2277extern void 2278efx_rx_fini( 2279 __in efx_nic_t *enp); 2280 2281#if EFSYS_OPT_RX_SCATTER 2282 __checkReturn efx_rc_t 2283efx_rx_scatter_enable( 2284 __in efx_nic_t *enp, 2285 __in unsigned int buf_size); 2286#endif /* EFSYS_OPT_RX_SCATTER */ 2287 2288/* Handle to represent use of the default RSS context. */ 2289#define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2290 2291#if EFSYS_OPT_RX_SCALE 2292 2293typedef enum efx_rx_hash_alg_e { 2294 EFX_RX_HASHALG_LFSR = 0, 2295 EFX_RX_HASHALG_TOEPLITZ, 2296 EFX_RX_HASHALG_PACKED_STREAM, 2297 EFX_RX_NHASHALGS 2298} efx_rx_hash_alg_t; 2299 2300/* 2301 * Legacy hash type flags. 2302 * 2303 * They represent standard tuples for distinct traffic classes. 2304 */ 2305#define EFX_RX_HASH_IPV4 (1U << 0) 2306#define EFX_RX_HASH_TCPIPV4 (1U << 1) 2307#define EFX_RX_HASH_IPV6 (1U << 2) 2308#define EFX_RX_HASH_TCPIPV6 (1U << 3) 2309 2310#define EFX_RX_HASH_LEGACY_MASK \ 2311 (EFX_RX_HASH_IPV4 | \ 2312 EFX_RX_HASH_TCPIPV4 | \ 2313 EFX_RX_HASH_IPV6 | \ 2314 EFX_RX_HASH_TCPIPV6) 2315 2316/* 2317 * The type of the argument used by efx_rx_scale_mode_set() to 2318 * provide a means for the client drivers to configure hashing. 2319 * 2320 * A properly constructed value can either be: 2321 * - a combination of legacy flags 2322 * - a combination of EFX_RX_HASH() flags 2323 */ 2324typedef uint32_t efx_rx_hash_type_t; 2325 2326typedef enum efx_rx_hash_support_e { 2327 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2328 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2329} efx_rx_hash_support_t; 2330 2331#define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2332#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2333#define EFX_MAXRSS 64 /* RX indirection entry range */ 2334#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2335 2336typedef enum efx_rx_scale_context_type_e { 2337 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2338 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2339 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2340} efx_rx_scale_context_type_t; 2341 2342/* 2343 * Traffic classes eligible for hash computation. 2344 * 2345 * Select packet headers used in computing the receive hash. 2346 * This uses the same encoding as the RSS_MODES field of 2347 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2348 */ 2349#define EFX_RX_CLASS_IPV4_TCP_LBN 8 2350#define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2351#define EFX_RX_CLASS_IPV4_UDP_LBN 12 2352#define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2353#define EFX_RX_CLASS_IPV4_LBN 16 2354#define EFX_RX_CLASS_IPV4_WIDTH 4 2355#define EFX_RX_CLASS_IPV6_TCP_LBN 20 2356#define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2357#define EFX_RX_CLASS_IPV6_UDP_LBN 24 2358#define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2359#define EFX_RX_CLASS_IPV6_LBN 28 2360#define EFX_RX_CLASS_IPV6_WIDTH 4 2361 2362#define EFX_RX_NCLASSES 6 2363 2364/* 2365 * Ancillary flags used to construct generic hash tuples. 2366 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2367 */ 2368#define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2369#define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2370#define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2371#define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2372 2373/* 2374 * Generic hash tuples. 2375 * 2376 * They express combinations of packet fields 2377 * which can contribute to the hash value for 2378 * a particular traffic class. 2379 */ 2380#define EFX_RX_CLASS_HASH_DISABLE 0 2381 2382#define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2383#define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2384 2385#define EFX_RX_CLASS_HASH_2TUPLE \ 2386 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2387 EFX_RX_CLASS_HASH_DST_ADDR) 2388 2389#define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2390 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2391 EFX_RX_CLASS_HASH_SRC_PORT) 2392 2393#define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2394 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2395 EFX_RX_CLASS_HASH_DST_PORT) 2396 2397#define EFX_RX_CLASS_HASH_4TUPLE \ 2398 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2399 EFX_RX_CLASS_HASH_DST_ADDR | \ 2400 EFX_RX_CLASS_HASH_SRC_PORT | \ 2401 EFX_RX_CLASS_HASH_DST_PORT) 2402 2403#define EFX_RX_CLASS_HASH_NTUPLES 7 2404 2405/* 2406 * Hash flag constructor. 2407 * 2408 * Resulting flags encode hash tuples for specific traffic classes. 2409 * The client drivers are encouraged to use these flags to form 2410 * a hash type value. 2411 */ 2412#define EFX_RX_HASH(_class, _tuple) \ 2413 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2414 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2415 2416/* 2417 * The maximum number of EFX_RX_HASH() flags. 2418 */ 2419#define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2420 2421extern __checkReturn efx_rc_t 2422efx_rx_scale_hash_flags_get( 2423 __in efx_nic_t *enp, 2424 __in efx_rx_hash_alg_t hash_alg, 2425 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2426 __in unsigned int max_nflags, 2427 __out unsigned int *nflagsp); 2428 2429extern __checkReturn efx_rc_t 2430efx_rx_hash_default_support_get( 2431 __in efx_nic_t *enp, 2432 __out efx_rx_hash_support_t *supportp); 2433 2434extern __checkReturn efx_rc_t 2435efx_rx_scale_default_support_get( 2436 __in efx_nic_t *enp, 2437 __out efx_rx_scale_context_type_t *typep); 2438 2439extern __checkReturn efx_rc_t 2440efx_rx_scale_context_alloc( 2441 __in efx_nic_t *enp, 2442 __in efx_rx_scale_context_type_t type, 2443 __in uint32_t num_queues, 2444 __out uint32_t *rss_contextp); 2445 2446extern __checkReturn efx_rc_t 2447efx_rx_scale_context_free( 2448 __in efx_nic_t *enp, 2449 __in uint32_t rss_context); 2450 2451extern __checkReturn efx_rc_t 2452efx_rx_scale_mode_set( 2453 __in efx_nic_t *enp, 2454 __in uint32_t rss_context, 2455 __in efx_rx_hash_alg_t alg, 2456 __in efx_rx_hash_type_t type, 2457 __in boolean_t insert); 2458 2459extern __checkReturn efx_rc_t 2460efx_rx_scale_tbl_set( 2461 __in efx_nic_t *enp, 2462 __in uint32_t rss_context, 2463 __in_ecount(n) unsigned int *table, 2464 __in size_t n); 2465 2466extern __checkReturn efx_rc_t 2467efx_rx_scale_key_set( 2468 __in efx_nic_t *enp, 2469 __in uint32_t rss_context, 2470 __in_ecount(n) uint8_t *key, 2471 __in size_t n); 2472 2473extern __checkReturn uint32_t 2474efx_pseudo_hdr_hash_get( 2475 __in efx_rxq_t *erp, 2476 __in efx_rx_hash_alg_t func, 2477 __in uint8_t *buffer); 2478 2479#endif /* EFSYS_OPT_RX_SCALE */ 2480 2481extern __checkReturn efx_rc_t 2482efx_pseudo_hdr_pkt_length_get( 2483 __in efx_rxq_t *erp, 2484 __in uint8_t *buffer, 2485 __out uint16_t *pkt_lengthp); 2486 2487#define EFX_RXQ_MAXNDESCS 4096 2488#define EFX_RXQ_MINNDESCS 512 2489 2490#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2491#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2492#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2493#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2494 2495typedef enum efx_rxq_type_e { 2496 EFX_RXQ_TYPE_DEFAULT, 2497 EFX_RXQ_TYPE_PACKED_STREAM, 2498 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2499 EFX_RXQ_NTYPES 2500} efx_rxq_type_t; 2501 2502/* 2503 * Dummy flag to be used instead of 0 to make it clear that the argument 2504 * is receive queue flags. 2505 */ 2506#define EFX_RXQ_FLAG_NONE 0x0 2507#define EFX_RXQ_FLAG_SCATTER 0x1 2508/* 2509 * If tunnels are supported and Rx event can provide information about 2510 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2511 * full-feature firmware variant running), outer classes are requested by 2512 * default. However, if the driver supports tunnels, the flag allows to 2513 * request inner classes which are required to be able to interpret inner 2514 * Rx checksum offload results. 2515 */ 2516#define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2517 2518extern __checkReturn efx_rc_t 2519efx_rx_qcreate( 2520 __in efx_nic_t *enp, 2521 __in unsigned int index, 2522 __in unsigned int label, 2523 __in efx_rxq_type_t type, 2524 __in efsys_mem_t *esmp, 2525 __in size_t ndescs, 2526 __in uint32_t id, 2527 __in unsigned int flags, 2528 __in efx_evq_t *eep, 2529 __deref_out efx_rxq_t **erpp); 2530 2531#if EFSYS_OPT_RX_PACKED_STREAM 2532 2533#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2534#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2535#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2536#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2537#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2538 2539extern __checkReturn efx_rc_t 2540efx_rx_qcreate_packed_stream( 2541 __in efx_nic_t *enp, 2542 __in unsigned int index, 2543 __in unsigned int label, 2544 __in uint32_t ps_buf_size, 2545 __in efsys_mem_t *esmp, 2546 __in size_t ndescs, 2547 __in efx_evq_t *eep, 2548 __deref_out efx_rxq_t **erpp); 2549 2550#endif 2551 2552#if EFSYS_OPT_RX_ES_SUPER_BUFFER 2553 2554/* Maximum head-of-line block timeout in nanoseconds */ 2555#define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 2556 2557extern __checkReturn efx_rc_t 2558efx_rx_qcreate_es_super_buffer( 2559 __in efx_nic_t *enp, 2560 __in unsigned int index, 2561 __in unsigned int label, 2562 __in uint32_t n_bufs_per_desc, 2563 __in uint32_t max_dma_len, 2564 __in uint32_t buf_stride, 2565 __in uint32_t hol_block_timeout, 2566 __in efsys_mem_t *esmp, 2567 __in size_t ndescs, 2568 __in unsigned int flags, 2569 __in efx_evq_t *eep, 2570 __deref_out efx_rxq_t **erpp); 2571 2572#endif 2573 2574typedef struct efx_buffer_s { 2575 efsys_dma_addr_t eb_addr; 2576 size_t eb_size; 2577 boolean_t eb_eop; 2578} efx_buffer_t; 2579 2580typedef struct efx_desc_s { 2581 efx_qword_t ed_eq; 2582} efx_desc_t; 2583 2584extern void 2585efx_rx_qpost( 2586 __in efx_rxq_t *erp, 2587 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2588 __in size_t size, 2589 __in unsigned int ndescs, 2590 __in unsigned int completed, 2591 __in unsigned int added); 2592 2593extern void 2594efx_rx_qpush( 2595 __in efx_rxq_t *erp, 2596 __in unsigned int added, 2597 __inout unsigned int *pushedp); 2598 2599#if EFSYS_OPT_RX_PACKED_STREAM 2600 2601extern void 2602efx_rx_qpush_ps_credits( 2603 __in efx_rxq_t *erp); 2604 2605extern __checkReturn uint8_t * 2606efx_rx_qps_packet_info( 2607 __in efx_rxq_t *erp, 2608 __in uint8_t *buffer, 2609 __in uint32_t buffer_length, 2610 __in uint32_t current_offset, 2611 __out uint16_t *lengthp, 2612 __out uint32_t *next_offsetp, 2613 __out uint32_t *timestamp); 2614#endif 2615 2616extern __checkReturn efx_rc_t 2617efx_rx_qflush( 2618 __in efx_rxq_t *erp); 2619 2620extern void 2621efx_rx_qenable( 2622 __in efx_rxq_t *erp); 2623 2624extern void 2625efx_rx_qdestroy( 2626 __in efx_rxq_t *erp); 2627 2628/* TX */ 2629 2630typedef struct efx_txq_s efx_txq_t; 2631 2632#if EFSYS_OPT_QSTATS 2633 2634/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2635typedef enum efx_tx_qstat_e { 2636 TX_POST, 2637 TX_POST_PIO, 2638 TX_NQSTATS 2639} efx_tx_qstat_t; 2640 2641/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2642 2643#endif /* EFSYS_OPT_QSTATS */ 2644 2645extern __checkReturn efx_rc_t 2646efx_tx_init( 2647 __in efx_nic_t *enp); 2648 2649extern void 2650efx_tx_fini( 2651 __in efx_nic_t *enp); 2652 2653#define EFX_TXQ_MINNDESCS 512 2654 2655#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2656#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2657#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2658 2659#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2660 2661#define EFX_TXQ_CKSUM_IPV4 0x0001 2662#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2663#define EFX_TXQ_FATSOV2 0x0004 2664#define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2665#define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2666 2667extern __checkReturn efx_rc_t 2668efx_tx_qcreate( 2669 __in efx_nic_t *enp, 2670 __in unsigned int index, 2671 __in unsigned int label, 2672 __in efsys_mem_t *esmp, 2673 __in size_t n, 2674 __in uint32_t id, 2675 __in uint16_t flags, 2676 __in efx_evq_t *eep, 2677 __deref_out efx_txq_t **etpp, 2678 __out unsigned int *addedp); 2679 2680extern __checkReturn efx_rc_t 2681efx_tx_qpost( 2682 __in efx_txq_t *etp, 2683 __in_ecount(ndescs) efx_buffer_t *eb, 2684 __in unsigned int ndescs, 2685 __in unsigned int completed, 2686 __inout unsigned int *addedp); 2687 2688extern __checkReturn efx_rc_t 2689efx_tx_qpace( 2690 __in efx_txq_t *etp, 2691 __in unsigned int ns); 2692 2693extern void 2694efx_tx_qpush( 2695 __in efx_txq_t *etp, 2696 __in unsigned int added, 2697 __in unsigned int pushed); 2698 2699extern __checkReturn efx_rc_t 2700efx_tx_qflush( 2701 __in efx_txq_t *etp); 2702 2703extern void 2704efx_tx_qenable( 2705 __in efx_txq_t *etp); 2706 2707extern __checkReturn efx_rc_t 2708efx_tx_qpio_enable( 2709 __in efx_txq_t *etp); 2710 2711extern void 2712efx_tx_qpio_disable( 2713 __in efx_txq_t *etp); 2714 2715extern __checkReturn efx_rc_t 2716efx_tx_qpio_write( 2717 __in efx_txq_t *etp, 2718 __in_ecount(buf_length) uint8_t *buffer, 2719 __in size_t buf_length, 2720 __in size_t pio_buf_offset); 2721 2722extern __checkReturn efx_rc_t 2723efx_tx_qpio_post( 2724 __in efx_txq_t *etp, 2725 __in size_t pkt_length, 2726 __in unsigned int completed, 2727 __inout unsigned int *addedp); 2728 2729extern __checkReturn efx_rc_t 2730efx_tx_qdesc_post( 2731 __in efx_txq_t *etp, 2732 __in_ecount(n) efx_desc_t *ed, 2733 __in unsigned int n, 2734 __in unsigned int completed, 2735 __inout unsigned int *addedp); 2736 2737extern void 2738efx_tx_qdesc_dma_create( 2739 __in efx_txq_t *etp, 2740 __in efsys_dma_addr_t addr, 2741 __in size_t size, 2742 __in boolean_t eop, 2743 __out efx_desc_t *edp); 2744 2745extern void 2746efx_tx_qdesc_tso_create( 2747 __in efx_txq_t *etp, 2748 __in uint16_t ipv4_id, 2749 __in uint32_t tcp_seq, 2750 __in uint8_t tcp_flags, 2751 __out efx_desc_t *edp); 2752 2753/* Number of FATSOv2 option descriptors */ 2754#define EFX_TX_FATSOV2_OPT_NDESCS 2 2755 2756/* Maximum number of DMA segments per TSO packet (not superframe) */ 2757#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2758 2759extern void 2760efx_tx_qdesc_tso2_create( 2761 __in efx_txq_t *etp, 2762 __in uint16_t ipv4_id, 2763 __in uint16_t outer_ipv4_id, 2764 __in uint32_t tcp_seq, 2765 __in uint16_t tcp_mss, 2766 __out_ecount(count) efx_desc_t *edp, 2767 __in int count); 2768 2769extern void 2770efx_tx_qdesc_vlantci_create( 2771 __in efx_txq_t *etp, 2772 __in uint16_t tci, 2773 __out efx_desc_t *edp); 2774 2775extern void 2776efx_tx_qdesc_checksum_create( 2777 __in efx_txq_t *etp, 2778 __in uint16_t flags, 2779 __out efx_desc_t *edp); 2780 2781#if EFSYS_OPT_QSTATS 2782 2783#if EFSYS_OPT_NAMES 2784 2785extern const char * 2786efx_tx_qstat_name( 2787 __in efx_nic_t *etp, 2788 __in unsigned int id); 2789 2790#endif /* EFSYS_OPT_NAMES */ 2791 2792extern void 2793efx_tx_qstats_update( 2794 __in efx_txq_t *etp, 2795 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2796 2797#endif /* EFSYS_OPT_QSTATS */ 2798 2799extern void 2800efx_tx_qdestroy( 2801 __in efx_txq_t *etp); 2802 2803/* FILTER */ 2804 2805#if EFSYS_OPT_FILTER 2806 2807#define EFX_ETHER_TYPE_IPV4 0x0800 2808#define EFX_ETHER_TYPE_IPV6 0x86DD 2809 2810#define EFX_IPPROTO_TCP 6 2811#define EFX_IPPROTO_UDP 17 2812#define EFX_IPPROTO_GRE 47 2813 2814/* Use RSS to spread across multiple queues */ 2815#define EFX_FILTER_FLAG_RX_RSS 0x01 2816/* Enable RX scatter */ 2817#define EFX_FILTER_FLAG_RX_SCATTER 0x02 2818/* 2819 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2820 * May only be set by the filter implementation for each type. 2821 * A removal request will restore the automatic filter in its place. 2822 */ 2823#define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2824/* Filter is for RX */ 2825#define EFX_FILTER_FLAG_RX 0x08 2826/* Filter is for TX */ 2827#define EFX_FILTER_FLAG_TX 0x10 2828/* Set match flag on the received packet */ 2829#define EFX_FILTER_FLAG_ACTION_FLAG 0x20 2830/* Set match mark on the received packet */ 2831#define EFX_FILTER_FLAG_ACTION_MARK 0x40 2832 2833typedef uint8_t efx_filter_flags_t; 2834 2835/* 2836 * Flags which specify the fields to match on. The values are the same as in the 2837 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2838 */ 2839 2840/* Match by remote IP host address */ 2841#define EFX_FILTER_MATCH_REM_HOST 0x00000001 2842/* Match by local IP host address */ 2843#define EFX_FILTER_MATCH_LOC_HOST 0x00000002 2844/* Match by remote MAC address */ 2845#define EFX_FILTER_MATCH_REM_MAC 0x00000004 2846/* Match by remote TCP/UDP port */ 2847#define EFX_FILTER_MATCH_REM_PORT 0x00000008 2848/* Match by remote TCP/UDP port */ 2849#define EFX_FILTER_MATCH_LOC_MAC 0x00000010 2850/* Match by local TCP/UDP port */ 2851#define EFX_FILTER_MATCH_LOC_PORT 0x00000020 2852/* Match by Ether-type */ 2853#define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 2854/* Match by inner VLAN ID */ 2855#define EFX_FILTER_MATCH_INNER_VID 0x00000080 2856/* Match by outer VLAN ID */ 2857#define EFX_FILTER_MATCH_OUTER_VID 0x00000100 2858/* Match by IP transport protocol */ 2859#define EFX_FILTER_MATCH_IP_PROTO 0x00000200 2860/* Match by VNI or VSID */ 2861#define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 2862/* For encapsulated packets, match by inner frame local MAC address */ 2863#define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 2864/* For encapsulated packets, match all multicast inner frames */ 2865#define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 2866/* For encapsulated packets, match all unicast inner frames */ 2867#define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 2868/* 2869 * Match by encap type, this flag does not correspond to 2870 * the MCDI match flags and any unoccupied value may be used 2871 */ 2872#define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 2873/* Match otherwise-unmatched multicast and broadcast packets */ 2874#define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 2875/* Match otherwise-unmatched unicast packets */ 2876#define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 2877 2878typedef uint32_t efx_filter_match_flags_t; 2879 2880typedef enum efx_filter_priority_s { 2881 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2882 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2883 * address list or hardware 2884 * requirements. This may only be used 2885 * by the filter implementation for 2886 * each NIC type. */ 2887 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2888 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2889 * client (e.g. SR-IOV, HyperV VMQ etc.) 2890 */ 2891} efx_filter_priority_t; 2892 2893/* 2894 * FIXME: All these fields are assumed to be in little-endian byte order. 2895 * It may be better for some to be big-endian. See bug42804. 2896 */ 2897 2898typedef struct efx_filter_spec_s { 2899 efx_filter_match_flags_t efs_match_flags; 2900 uint8_t efs_priority; 2901 efx_filter_flags_t efs_flags; 2902 uint16_t efs_dmaq_id; 2903 uint32_t efs_rss_context; 2904 uint32_t efs_mark; 2905 /* Fields below here are hashed for software filter lookup */ 2906 uint16_t efs_outer_vid; 2907 uint16_t efs_inner_vid; 2908 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2909 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2910 uint16_t efs_ether_type; 2911 uint8_t efs_ip_proto; 2912 efx_tunnel_protocol_t efs_encap_type; 2913 uint16_t efs_loc_port; 2914 uint16_t efs_rem_port; 2915 efx_oword_t efs_rem_host; 2916 efx_oword_t efs_loc_host; 2917 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 2918 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 2919} efx_filter_spec_t; 2920 2921/* Default values for use in filter specifications */ 2922#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2923#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2924 2925extern __checkReturn efx_rc_t 2926efx_filter_init( 2927 __in efx_nic_t *enp); 2928 2929extern void 2930efx_filter_fini( 2931 __in efx_nic_t *enp); 2932 2933extern __checkReturn efx_rc_t 2934efx_filter_insert( 2935 __in efx_nic_t *enp, 2936 __inout efx_filter_spec_t *spec); 2937 2938extern __checkReturn efx_rc_t 2939efx_filter_remove( 2940 __in efx_nic_t *enp, 2941 __inout efx_filter_spec_t *spec); 2942 2943extern __checkReturn efx_rc_t 2944efx_filter_restore( 2945 __in efx_nic_t *enp); 2946 2947extern __checkReturn efx_rc_t 2948efx_filter_supported_filters( 2949 __in efx_nic_t *enp, 2950 __out_ecount(buffer_length) uint32_t *buffer, 2951 __in size_t buffer_length, 2952 __out size_t *list_lengthp); 2953 2954extern void 2955efx_filter_spec_init_rx( 2956 __out efx_filter_spec_t *spec, 2957 __in efx_filter_priority_t priority, 2958 __in efx_filter_flags_t flags, 2959 __in efx_rxq_t *erp); 2960 2961extern void 2962efx_filter_spec_init_tx( 2963 __out efx_filter_spec_t *spec, 2964 __in efx_txq_t *etp); 2965 2966extern __checkReturn efx_rc_t 2967efx_filter_spec_set_ipv4_local( 2968 __inout efx_filter_spec_t *spec, 2969 __in uint8_t proto, 2970 __in uint32_t host, 2971 __in uint16_t port); 2972 2973extern __checkReturn efx_rc_t 2974efx_filter_spec_set_ipv4_full( 2975 __inout efx_filter_spec_t *spec, 2976 __in uint8_t proto, 2977 __in uint32_t lhost, 2978 __in uint16_t lport, 2979 __in uint32_t rhost, 2980 __in uint16_t rport); 2981 2982extern __checkReturn efx_rc_t 2983efx_filter_spec_set_eth_local( 2984 __inout efx_filter_spec_t *spec, 2985 __in uint16_t vid, 2986 __in const uint8_t *addr); 2987 2988extern void 2989efx_filter_spec_set_ether_type( 2990 __inout efx_filter_spec_t *spec, 2991 __in uint16_t ether_type); 2992 2993extern __checkReturn efx_rc_t 2994efx_filter_spec_set_uc_def( 2995 __inout efx_filter_spec_t *spec); 2996 2997extern __checkReturn efx_rc_t 2998efx_filter_spec_set_mc_def( 2999 __inout efx_filter_spec_t *spec); 3000 3001typedef enum efx_filter_inner_frame_match_e { 3002 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3003 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3004 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3005} efx_filter_inner_frame_match_t; 3006 3007extern __checkReturn efx_rc_t 3008efx_filter_spec_set_encap_type( 3009 __inout efx_filter_spec_t *spec, 3010 __in efx_tunnel_protocol_t encap_type, 3011 __in efx_filter_inner_frame_match_t inner_frame_match); 3012 3013extern __checkReturn efx_rc_t 3014efx_filter_spec_set_vxlan( 3015 __inout efx_filter_spec_t *spec, 3016 __in const uint8_t *vni, 3017 __in const uint8_t *inner_addr, 3018 __in const uint8_t *outer_addr); 3019 3020extern __checkReturn efx_rc_t 3021efx_filter_spec_set_geneve( 3022 __inout efx_filter_spec_t *spec, 3023 __in const uint8_t *vni, 3024 __in const uint8_t *inner_addr, 3025 __in const uint8_t *outer_addr); 3026 3027extern __checkReturn efx_rc_t 3028efx_filter_spec_set_nvgre( 3029 __inout efx_filter_spec_t *spec, 3030 __in const uint8_t *vsid, 3031 __in const uint8_t *inner_addr, 3032 __in const uint8_t *outer_addr); 3033 3034#if EFSYS_OPT_RX_SCALE 3035extern __checkReturn efx_rc_t 3036efx_filter_spec_set_rss_context( 3037 __inout efx_filter_spec_t *spec, 3038 __in uint32_t rss_context); 3039#endif 3040#endif /* EFSYS_OPT_FILTER */ 3041 3042/* HASH */ 3043 3044extern __checkReturn uint32_t 3045efx_hash_dwords( 3046 __in_ecount(count) uint32_t const *input, 3047 __in size_t count, 3048 __in uint32_t init); 3049 3050extern __checkReturn uint32_t 3051efx_hash_bytes( 3052 __in_ecount(length) uint8_t const *input, 3053 __in size_t length, 3054 __in uint32_t init); 3055 3056#if EFSYS_OPT_LICENSING 3057 3058/* LICENSING */ 3059 3060typedef struct efx_key_stats_s { 3061 uint32_t eks_valid; 3062 uint32_t eks_invalid; 3063 uint32_t eks_blacklisted; 3064 uint32_t eks_unverifiable; 3065 uint32_t eks_wrong_node; 3066 uint32_t eks_licensed_apps_lo; 3067 uint32_t eks_licensed_apps_hi; 3068 uint32_t eks_licensed_features_lo; 3069 uint32_t eks_licensed_features_hi; 3070} efx_key_stats_t; 3071 3072extern __checkReturn efx_rc_t 3073efx_lic_init( 3074 __in efx_nic_t *enp); 3075 3076extern void 3077efx_lic_fini( 3078 __in efx_nic_t *enp); 3079 3080extern __checkReturn boolean_t 3081efx_lic_check_support( 3082 __in efx_nic_t *enp); 3083 3084extern __checkReturn efx_rc_t 3085efx_lic_update_licenses( 3086 __in efx_nic_t *enp); 3087 3088extern __checkReturn efx_rc_t 3089efx_lic_get_key_stats( 3090 __in efx_nic_t *enp, 3091 __out efx_key_stats_t *ksp); 3092 3093extern __checkReturn efx_rc_t 3094efx_lic_app_state( 3095 __in efx_nic_t *enp, 3096 __in uint64_t app_id, 3097 __out boolean_t *licensedp); 3098 3099extern __checkReturn efx_rc_t 3100efx_lic_get_id( 3101 __in efx_nic_t *enp, 3102 __in size_t buffer_size, 3103 __out uint32_t *typep, 3104 __out size_t *lengthp, 3105 __out_opt uint8_t *bufferp); 3106 3107extern __checkReturn efx_rc_t 3108efx_lic_find_start( 3109 __in efx_nic_t *enp, 3110 __in_bcount(buffer_size) 3111 caddr_t bufferp, 3112 __in size_t buffer_size, 3113 __out uint32_t *startp); 3114 3115extern __checkReturn efx_rc_t 3116efx_lic_find_end( 3117 __in efx_nic_t *enp, 3118 __in_bcount(buffer_size) 3119 caddr_t bufferp, 3120 __in size_t buffer_size, 3121 __in uint32_t offset, 3122 __out uint32_t *endp); 3123 3124extern __checkReturn __success(return != B_FALSE) boolean_t 3125efx_lic_find_key( 3126 __in efx_nic_t *enp, 3127 __in_bcount(buffer_size) 3128 caddr_t bufferp, 3129 __in size_t buffer_size, 3130 __in uint32_t offset, 3131 __out uint32_t *startp, 3132 __out uint32_t *lengthp); 3133 3134extern __checkReturn __success(return != B_FALSE) boolean_t 3135efx_lic_validate_key( 3136 __in efx_nic_t *enp, 3137 __in_bcount(length) caddr_t keyp, 3138 __in uint32_t length); 3139 3140extern __checkReturn efx_rc_t 3141efx_lic_read_key( 3142 __in efx_nic_t *enp, 3143 __in_bcount(buffer_size) 3144 caddr_t bufferp, 3145 __in size_t buffer_size, 3146 __in uint32_t offset, 3147 __in uint32_t length, 3148 __out_bcount_part(key_max_size, *lengthp) 3149 caddr_t keyp, 3150 __in size_t key_max_size, 3151 __out uint32_t *lengthp); 3152 3153extern __checkReturn efx_rc_t 3154efx_lic_write_key( 3155 __in efx_nic_t *enp, 3156 __in_bcount(buffer_size) 3157 caddr_t bufferp, 3158 __in size_t buffer_size, 3159 __in uint32_t offset, 3160 __in_bcount(length) caddr_t keyp, 3161 __in uint32_t length, 3162 __out uint32_t *lengthp); 3163 3164 __checkReturn efx_rc_t 3165efx_lic_delete_key( 3166 __in efx_nic_t *enp, 3167 __in_bcount(buffer_size) 3168 caddr_t bufferp, 3169 __in size_t buffer_size, 3170 __in uint32_t offset, 3171 __in uint32_t length, 3172 __in uint32_t end, 3173 __out uint32_t *deltap); 3174 3175extern __checkReturn efx_rc_t 3176efx_lic_create_partition( 3177 __in efx_nic_t *enp, 3178 __in_bcount(buffer_size) 3179 caddr_t bufferp, 3180 __in size_t buffer_size); 3181 3182extern __checkReturn efx_rc_t 3183efx_lic_finish_partition( 3184 __in efx_nic_t *enp, 3185 __in_bcount(buffer_size) 3186 caddr_t bufferp, 3187 __in size_t buffer_size); 3188 3189#endif /* EFSYS_OPT_LICENSING */ 3190 3191/* TUNNEL */ 3192 3193#if EFSYS_OPT_TUNNEL 3194 3195extern __checkReturn efx_rc_t 3196efx_tunnel_init( 3197 __in efx_nic_t *enp); 3198 3199extern void 3200efx_tunnel_fini( 3201 __in efx_nic_t *enp); 3202 3203/* 3204 * For overlay network encapsulation using UDP, the firmware needs to know 3205 * the configured UDP port for the overlay so it can decode encapsulated 3206 * frames correctly. 3207 * The UDP port/protocol list is global. 3208 */ 3209 3210extern __checkReturn efx_rc_t 3211efx_tunnel_config_udp_add( 3212 __in efx_nic_t *enp, 3213 __in uint16_t port /* host/cpu-endian */, 3214 __in efx_tunnel_protocol_t protocol); 3215 3216extern __checkReturn efx_rc_t 3217efx_tunnel_config_udp_remove( 3218 __in efx_nic_t *enp, 3219 __in uint16_t port /* host/cpu-endian */, 3220 __in efx_tunnel_protocol_t protocol); 3221 3222extern void 3223efx_tunnel_config_clear( 3224 __in efx_nic_t *enp); 3225 3226/** 3227 * Apply tunnel UDP ports configuration to hardware. 3228 * 3229 * EAGAIN is returned if hardware will be reset (datapath and management CPU 3230 * reboot). 3231 */ 3232extern __checkReturn efx_rc_t 3233efx_tunnel_reconfigure( 3234 __in efx_nic_t *enp); 3235 3236#endif /* EFSYS_OPT_TUNNEL */ 3237 3238#if EFSYS_OPT_FW_SUBVARIANT_AWARE 3239 3240/** 3241 * Firmware subvariant choice options. 3242 * 3243 * It may be switched to no Tx checksum if attached drivers are either 3244 * preboot or firmware subvariant aware and no VIS are allocated. 3245 * If may be always switched to default explicitly using set request or 3246 * implicitly if unaware driver is attaching. If switching is done when 3247 * a driver is attached, it gets MC_REBOOT event and should recreate its 3248 * datapath. 3249 * 3250 * See SF-119419-TC DPDK Firmware Driver Interface and 3251 * SF-109306-TC EF10 for Driver Writers for details. 3252 */ 3253typedef enum efx_nic_fw_subvariant_e { 3254 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3255 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3256 EFX_NIC_FW_SUBVARIANT_NTYPES 3257} efx_nic_fw_subvariant_t; 3258 3259extern __checkReturn efx_rc_t 3260efx_nic_get_fw_subvariant( 3261 __in efx_nic_t *enp, 3262 __out efx_nic_fw_subvariant_t *subvariantp); 3263 3264extern __checkReturn efx_rc_t 3265efx_nic_set_fw_subvariant( 3266 __in efx_nic_t *enp, 3267 __in efx_nic_fw_subvariant_t subvariant); 3268 3269#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3270 3271typedef enum efx_phy_fec_type_e { 3272 EFX_PHY_FEC_NONE = 0, 3273 EFX_PHY_FEC_BASER, 3274 EFX_PHY_FEC_RS 3275} efx_phy_fec_type_t; 3276 3277extern __checkReturn efx_rc_t 3278efx_phy_fec_type_get( 3279 __in efx_nic_t *enp, 3280 __out efx_phy_fec_type_t *typep); 3281 3282typedef struct efx_phy_link_state_s { 3283 uint32_t epls_adv_cap_mask; 3284 uint32_t epls_lp_cap_mask; 3285 uint32_t epls_ld_cap_mask; 3286 unsigned int epls_fcntl; 3287 efx_phy_fec_type_t epls_fec; 3288 efx_link_mode_t epls_link_mode; 3289} efx_phy_link_state_t; 3290 3291extern __checkReturn efx_rc_t 3292efx_phy_link_state_get( 3293 __in efx_nic_t *enp, 3294 __out efx_phy_link_state_t *eplsp); 3295 3296#ifdef __cplusplus 3297} 3298#endif 3299 3300#endif /* _SYS_EFX_H */ 3301