| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 363 const TargetRegisterClass *DefRC,
368 if (DefRC == SrcRC)
374 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
382 std::swap(DefRC, SrcRC);
387 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
390 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
393 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
398 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
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| H A D | DetectDeadLanes.cpp | 373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); local
387 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
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| H A D | PeepholeOptimizer.cpp | 671 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); local
734 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC,
1234 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); local
1235 Register NewVReg = MRI->createVirtualRegister(DefRC);
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| H A D | RegisterCoalescer.cpp | 1292 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); local
1304 if (!DefRC->contains(NewDstReg))
1335 TRI->getCommonSubClass(DefRC, DstRC);
1384 if (DefRC != nullptr) {
1386 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
1388 NewRC = TRI->getCommonSubClass(NewRC, DefRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | X86RegisterInfo.cpp | 213 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, argument
220 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
224 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
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| H A D | X86SpeculativeLoadHardening.cpp | 1967 auto *DefRC = MRI->getRegClass(OldDefReg); local
1972 Register UnhardenedReg = MRI->createVirtualRegister(DefRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 429 const TargetRegisterClass *DefRC = nullptr; local
431 DefRC = TRI.getRegClass(DestReg);
433 DefRC = getRegClassForTypeOnBank(DestReg, MRI);
436 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 194 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | AMDGPUInstructionSelector.cpp | 219 const TargetRegisterClass *DefRC local
221 if (!DefRC) {
228 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI);
229 if (!DefRC) {
237 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);
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| H A D | SIRegisterInfo.cpp | 1678 const TargetRegisterClass *DefRC,
1698 return getCommonSubClass(DefRC, SrcRC) != nullptr;
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 543 // For a copy-like instruction that defines a register of class DefRC with
547 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1960 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); local
1961 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
1962 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1818 const TargetRegisterClass *DefRC local
1820 if (!DefRC) {
1826 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
1827 if (!DefRC) {
1835 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
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