Searched refs:DRC (Results 1 - 7 of 7) sorted by relevance
/freebsd-13-stable/sys/dev/sound/macio/ |
H A D | snapper.c | 194 u_char DRC[6]; member in struct:snapper_reg 225 { 1, 0, 0, 0, 0, 0 }, /* DRC */ 256 sizeof snapper_initdata.DRC, /* 0x02 */ 408 snapper_write(sc, SNAPPER_DRC, snapper_initdata.DRC);
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H A D | tumbler.c | 175 #define TUMBLER_DRC_ENABLE 0x01 /* enable DRC */ 184 u_char DRC[2]; member in struct:tumbler_reg 207 { TUMBLER_DRC_COMP_31, TUMBLER_DRC_DEFL_TH }, /* DRC */ 230 sizeof tumbler_initdata.DRC, /* 0x02 */ 360 tumbler_write(sc, TUMBLER_DRC, tumbler_initdata.DRC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR, 778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, 781 switch (DRC->getID()) { 802 Register MuxR = MRI->createVirtualRegister(DRC); 777 buildMux(MachineBasicBlock *B, MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) argument
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H A D | HexagonBitSimplify.cpp | 932 auto *DRC = getFinalVRegClass(RD, MRI); 933 if (!DRC) 936 return DRC == getFinalVRegClass(RS, MRI); 1480 const BitTracker::RegisterCell &DRC = BT.lookup(DR); 1481 if (HBS::getConst(DRC, 0, DRC.width(), U)) { 1488 BT.put(ImmReg, DRC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineVerifier.cpp | 1676 if (const TargetRegisterClass *DRC = 1678 if (!DRC->contains(Reg)) { 1681 << TRI->getRegClassName(DRC) << " register.\n"; 1785 if (const TargetRegisterClass *DRC = 1794 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); 1795 if (!DRC) { 1800 if (!RC->hasSuperClassEq(DRC)) { 1802 errs() << "Expected a " << TRI->getRegClassName(DRC)
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H A D | MachineSink.cpp | 232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); local 233 if (SRC != DRC)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 4262 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); local 4269 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); 4270 if (!DRC) 4273 return RC->hasSuperClassEq(DRC);
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