Searched refs:Cycles (Results 1 - 25 of 28) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
44 unsigned int Cycles; member in struct:__anon4460::VisitedBBInfo
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles) argument
48 : HasReturn(HasReturn), Cycles(Cycles) {}
76 unsigned int Cycles = 0);
79 unsigned int &Cycles);
135 unsigned Cycles = I->second; local
142 if (Cycles < Threshol
165 findReturns(MachineBasicBlock *MBB, unsigned int Cycles) argument
189 cyclesUntilReturn(MachineBasicBlock *MBB, unsigned int &Cycles) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) {
25 CRD.Cycles = Cycles;
26 DependentWriteCyclesLeft = Cycles;
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) { argument
40 if (TotalCycles < Cycles) {
43 CRD.Cycles = Cycles;
44 TotalCycles = Cycles;
126 << getRegisterID() << ", Cycles Lef
21 writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) argument
[all...]
H A DPipeline.cpp45 ++Cycles;
48 return Cycles;
86 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n');
92 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n");
H A DInstrBuilder.cpp68 if (!PRE->Cycles) {
88 CycleSegment RCy(0, PRE->Cycles, false);
92 SuperResources[Super] += PRE->Cycles;
324 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
352 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DPipeline.h57 unsigned Cycles; member in class:llvm::mca::Pipeline
65 Pipeline() : Cycles(0) {}
H A DSupport.h55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1) argument
56 : Numerator(Cycles), Denominator(ResourceUnits) {}
H A DInstruction.h90 unsigned Cycles; member in struct:llvm::mca::CriticalDependency
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
320 void subtract(unsigned Cycles) { argument
321 assert(End >= Cycles);
322 End -= Cycles;
340 ResourceUsage(CycleSegment Cycles, unsigned Units = 1) argument
341 : CS(Cycles), NumUnits(Units) {}
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h66 uint16_t Cycles; member in struct:llvm::MCWriteProcResEntry
69 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
79 int16_t Cycles; member in struct:llvm::MCWriteLatencyEntry
83 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
98 int Cycles; member in struct:llvm::MCReadAdvanceEntry
102 && Cycles == Other.Cycles;
H A DMCSubtargetInfo.h190 return I->Cycles;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); local
42 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits)));
49 // Uniformly distribute Cycles across all of the units.
57 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits)));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp49 if (WLEntry->Cycles < 0)
50 return WLEntry->Cycles;
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
95 if (!I->Cycles)
98 double Temp = NumUnits * 1.0 / I->Cycles;
163 DelayCycles = std::min(DelayCycles, E.Cycles);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h122 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); local
123 if (CriticalPredecessor.Cycles < Cycles) {
125 CriticalPredecessor.Cycles = Cycles;
182 if (isWaiting() && CriticalPredecessor.Cycles)
183 CriticalPredecessor.Cycles--;
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles)
24 MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0), WaitTime(S.size()),
119 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, argument
124 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize);
266 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { argument
268 if (Cycles >= 10) {
270 for (unsigned I = 0; I <= Cycles; ++I) {
281 for (unsigned I = 0; I <= Cycles; ++I) {
20 TimelineView(const MCSubtargetInfo &sti, MCInstPrinter &Printer, llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations, unsigned Cycles) argument
H A DTimelineView.h170 unsigned Cycles);
H A DBottleneckAnalysis.cpp514 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID);
521 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles);
527 if (RegDep.Cycles) {
528 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID);
530 addRegisterDep(From, To, RegDep.RegID, Cycles);
534 if (MemDep.Cycles) {
535 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID);
537 addMemoryDep(From, To, Cycles);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
308 int Cycles = Stage->getValueAsInt("Cycles"); local
309 ItinString += " { " + itostr(Cycles) + ", ";
937 std::vector<int64_t> &Cycles,
939 assert(PRVec.size() == Cycles.size() && "failed precondition");
959 Cycles.push_back(Cycles[i]);
975 Cycles.push_back(Cycles[
936 ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles, const CodeGenProcModel &PM) argument
1106 std::vector<int64_t> Cycles = local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp126 static unsigned capLatency(int Cycles) { argument
127 return Cycles >= 0 ? Cycles : 1000;
224 unsigned Latency = capLatency(WLEntry->Cycles);
H A DMachineTraceMetrics.cpp130 PRCycles[PI->ProcResourceIdx] += PI->Cycles;
583 Cycles.erase(&I);
776 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
801 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
809 InstrCycles &MICycles = Cycles[&UseMI];
1082 unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0;
1121 InstrCycles &MICycles = Cycles[&MI];
1237 unsigned Cycles = 0;
1247 Cycles +=
1248 (PI->Cycles * T
[all...]
H A DMachineScheduler.cpp1943 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1989 unsigned Cycles) {
1996 NextUnreserved += Cycles;
2004 SchedBoundary::getNextResourceCycle(unsigned PIdx, unsigned Cycles) { argument
2014 unsigned NextUnreserved = getNextResourceCycleByInstance(I, Cycles);
2063 unsigned Cycles = PE.Cycles; local
2065 std::tie(NRCycle, InstanceIdx) = getNextResourceCycle(ResIdx, Cycles);
2068 MaxObservedStall = std::max(Cycles, MaxObservedStall);
2210 /// \param Cycles indicate
1988 getNextResourceCycleByInstance(unsigned InstanceIdx, unsigned Cycles) argument
2216 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp190 if (PI->Cycles > 1)
191 OS << "(" << PI->Cycles << "cyc)";
304 CurrCounter += PI->Cycles;
404 Cost = PI->Cycles;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h299 return TE.Cycles.lookup(&MI);
325 DenseMap<const MachineInstr*, InstrCycles> Cycles; member in class:llvm::MachineTraceMetrics::Ensemble
403 // Cycles consumed on each processor resource per block.
H A DMachineScheduler.h752 unsigned Cycles);
755 unsigned Cycles);
778 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp281 Expected<unsigned> Cycles = P.run();
282 if (!Cycles) {
283 WithColor::error() << toString(Cycles.takeError());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp406 unsigned Cycles[3] = { 2, 1, 0};
407 return Cycles[Op];
410 unsigned Cycles[3] = { 1, 2, 2};
411 return Cycles[Op];
414 unsigned Cycles[3] = { 2, 1, 2};
415 return Cycles[Op];
418 unsigned Cycles[3] = { 2, 2, 1};
419 return Cycles[Op];
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp222 Latency = std::max(Latency, WLEntry->Cycles);

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