Lines Matching refs:Cycles
111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
308 int Cycles = Stage->getValueAsInt("Cycles");
309 ItinString += " { " + itostr(Cycles) + ", ";
937 std::vector<int64_t> &Cycles,
939 assert(PRVec.size() == Cycles.size() && "failed precondition");
959 Cycles.push_back(Cycles[i]);
975 Cycles.push_back(Cycles[i]);
1076 WLEntry.Cycles = 0;
1097 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
1106 std::vector<int64_t> Cycles =
1109 if (Cycles.empty()) {
1112 Cycles.resize(PRVec.size(), 1);
1113 } else if (Cycles.size() != PRVec.size()) {
1121 .concat(Twine(Cycles.size())));
1124 ExpandProcResources(PRVec, Cycles, ProcModel);
1131 WPREntry.Cycles = Cycles[PRIdx];
1140 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
1178 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1248 OS << "\n// {ProcResourceIdx, Cycles}\n"
1256 << format("%2d", WPREntry.Cycles) << "}";
1264 OS << "\n// {Cycles, WriteResourceID}\n"
1271 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1280 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1289 << format("%2d", RAEntry.Cycles) << "}";