Searched refs:AR5312_SYSREG_BASE (Results 1 - 4 of 4) sorted by relevance

/freebsd-13-stable/sys/mips/atheros/ar531x/
H A Dar5312_chip.c90 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL);
114 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL,
139 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR);
140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE);
141 // ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_WDOG_CTL, 0);
142 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0);
144 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE,
145 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) |
155 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL);
H A Dapb.c107 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
109 ATH_WRITE_REG(AR5312_SYSREG_BASE
126 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
128 ATH_WRITE_REG(AR5312_SYSREG_BASE +
257 ATH_WRITE_REG(AR5312_SYSREG_BASE
492 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
502 ATH_WRITE_REG(AR5312_SYSREG_BASE +
510 ATH_READ_REG(AR5312_SYSREG_BASE +
512 ATH_READ_REG(AR5312_SYSREG_BASE +
545 intr = ATH_READ_REG(AR5312_SYSREG_BASE
[all...]
H A Dar5312reg.h60 #define AR5312_SYSREG_BASE 0x1C003000 macro
185 #define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE)
186 #define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v)
H A Dar5315_setup.c133 ver = ATH_READ_REG(AR5312_SYSREG_BASE +

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